公开(公告)号：US5652172A

公开(公告)日：1997-07-29

申请号：US639679

申请日：1996-04-29

申请人： Peng Yung-Sung ,  An Min Chiang ,  Shau-Tsung Yu ,  Min-Yi Lin

发明人： Peng Yung-Sung ,  An Min Chiang ,  Shau-Tsung Yu ,  Min-Yi Lin

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/31105 ,  H01L21/31144 ,  H01L21/76804

摘要： A method for forming an aperture with a uniform void-free sidewall etch profile through a multi-layer insulator layer. There is formed upon a semiconductor substrate a multi-layer insulator layer which has a minimum of a first insulator layer and a second insulator layer. The second insulator layer is formed upon the first insulator layer. There is then etched through a first etch method a first aperture completely through the second insulator layer. The first etch method has: (1) a first perpendicular etch selectivity ratio for the second insulator layer with respect to the first insulator layer of at least about 4:1; and (2) a lateral:perpendicular etch selectivity ratio for the second insulator layer of from about 0.5:1 to about 1:1. The first aperture is then etched through a second etch method to form a second aperture completely through the second insulator layer and the first insulator layer. The second etch method has: (1) a second perpendicular etch selectivity ratio for the second insulator layer with respect to the first insulator layer of no greater than about 2:1; and (2) a lateral etch selectivity ratio of the second insulator layer with respect to the first insulator layer of from about 0.5:1 to about 1:1. The second aperture has a uniform void-free sidewall etch profile.

摘要翻译： 一种通过多层绝缘体层形成具有均匀无空隙侧壁蚀刻轮廓的孔的方法。 在半导体衬底上形成具有最小第一绝缘体层和第二绝缘体层的多层绝缘体层。 第二绝缘体层形成在第一绝缘体层上。 然后通过第一蚀刻方法蚀刻完全穿过第二绝缘体层的第一孔。 第一蚀刻方法具有：（1）第二绝缘体层相对于第一绝缘体层的第一垂直蚀刻选择比为至少约4:1; 和（2）第二绝缘体层的横向：垂直蚀刻选择比为约0.5:1至约1:1。 然后通过第二蚀刻方法蚀刻第一孔，以完全穿过第二绝缘体层和第一绝缘体层形成第二孔。 第二蚀刻方法具有：（1）第二绝缘体层相对于第一绝缘体层的第二垂直蚀刻选择比不大于约2:1; 和（2）第二绝缘体层相对于第一绝缘体层的横向蚀刻选择比为约0.5:1至约1:1。 第二孔具有均匀的无空隙侧壁蚀刻轮廓。

公开(公告)号：US06297554B1

公开(公告)日：2001-10-02

申请号：US09522931

申请日：2000-03-10

申请人： Min-Yi Lin

发明人： Min-Yi Lin

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved structure of a dielectric layer between two adjacent copper wiring lines is disclosed. The dielectric layer is composed of silicon oxide and the adjacent copper wiring lines are formed using a dual damascene process. The structure of the dielectric layer according to the present invention comprises at least one trench in the surface of the dielectric layer, an insulating layer in the trench and at least one void in the insulating layer. The void is used to reduce the effective dielectric constant as well as the parasitic capacitance of the dielectric layer.

摘要翻译： 公开了两个相邻的铜布线之间的电介质层的改进的结构。 电介质层由氧化硅构成，并且使用双镶嵌工艺形成相邻的铜布线。 根据本发明的电介质层的结构包括介电层表面中的至少一个沟槽，沟槽中的绝缘层和绝缘层中的至少一个空隙。 该空隙用于降低介电层的有效介电常数以及寄生电容。