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6 条记录 (耗时 0.012 秒)

    Narrow channel width effect modification in a shallow trench isolation device
    1.
    发明授权
    Narrow channel width effect modification in a shallow trench isolation device 有权
    窄沟道宽度效应修改在浅沟槽隔离器件中

    公开(公告)号：US07960286B2

    公开(公告)日：2011-06-14

    申请号：US12486515

    申请日：2009-06-17

    申请人： Ming-Han Liao ,  Tze-Liang Lee

    发明人： Ming-Han Liao ,  Tze-Liang Lee

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76237

    摘要： A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

    摘要翻译： 提供一种制造半导体结构的方法。 该方法包括在半导体衬底上形成硬掩模图案，其中硬掩模图案覆盖有源区; 在由所述硬掩模图案限定的开口内在所述半导体衬底中形成沟槽; 用电介质材料填充沟槽，导致沟槽隔离特征; 使用所述硬掩模图案对所述沟槽隔离特征进行离子注入以保护所述半导体衬底的有源区; 并且在执行离子注入之后去除硬掩模图案。

    STI STRESS MODULATION WITH ADDITIONAL IMPLANTATION AND NATURAL PAD SIN MASK
    2.
    发明申请
    STI STRESS MODULATION WITH ADDITIONAL IMPLANTATION AND NATURAL PAD SIN MASK 有权
    STI应力调整与附加植入和自然垫一起掩蔽

    公开(公告)号：US20100075480A1

    公开(公告)日：2010-03-25

    申请号：US12235329

    申请日：2008-09-22

    申请人： Ming-Han Liao ,  Tze-Liang Lee ,  Ling-Yen Yeh ,  Mong-Song Liang

    发明人： Ming-Han Liao ,  Tze-Liang Lee ,  Ling-Yen Yeh ,  Mong-Song Liang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

    摘要： A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

    摘要翻译： 提供一种制造半导体结构的方法。 该方法包括在半导体衬底上形成硬掩模图案，其中硬掩模图案覆盖有源区; 在由所述硬掩模图案限定的开口内在所述半导体衬底中形成沟槽; 用电介质材料填充沟槽，导致沟槽隔离特征; 使用所述硬掩模图案对所述沟槽隔离特征进行离子注入以保护所述半导体衬底的有源区; 并且在执行离子注入之后去除硬掩模图案。

    STI stress modulation with additional implantation and natural pad sin mask
    3.
    发明授权
    STI stress modulation with additional implantation and natural pad sin mask 有权
    STI应力调制与附加植入和天然衬垫sin掩模

    公开(公告)号：US07851328B2

    公开(公告)日：2010-12-14

    申请号：US12235329

    申请日：2008-09-22

    申请人： Ming-Han Liao ,  Tze-Liang Lee ,  Ling-Yen Yeh ,  Mong-Song Liang

    发明人： Ming-Han Liao ,  Tze-Liang Lee ,  Ling-Yen Yeh ,  Mong-Song Liang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

    摘要： A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

    摘要翻译： 提供一种制造半导体结构的方法。 该方法包括在半导体衬底上形成硬掩模图案，其中硬掩模图案覆盖有源区; 在由所述硬掩模图案限定的开口内在所述半导体衬底中形成沟槽; 用电介质材料填充沟槽，导致沟槽隔离特征; 使用所述硬掩模图案对所述沟槽隔离特征进行离子注入以保护所述半导体衬底的有源区; 并且在执行离子注入之后去除硬掩模图案。

    LIGHT-EMITTING ELEMENT WITH HETEROJUNCTION STRUCTURE
    4.
    发明申请
    LIGHT-EMITTING ELEMENT WITH HETEROJUNCTION STRUCTURE 审中-公开
    具有异常结构的发光元件

    公开(公告)号：US20070126014A1

    公开(公告)日：2007-06-07

    申请号：US11536025

    申请日：2006-09-28

    申请人： Ming-Han Liao ,  Cheng-Yeh Yu ,  Chee Wee Liu

    发明人： Ming-Han Liao ,  Cheng-Yeh Yu ,  Chee Wee Liu

    IPC分类号： H01L33/00 ,  H01L21/00

    CPC分类号： H01L33/34 ,  H01L33/0004

    摘要： A method for manufacturing a light-emitting element with a heterojunction of group IV is provided. The method comprises at least the steps of: (1) providing a silicon substrate having a first and a second surfaces; (2) forming a germanium layer on the first surface; (3) forming a cap layer on the germanium layer; (4) forming a oxidation layer on the cap layer; (5) forming a first conductive layer on the oxidation layer; (6) forming a second conductive layer on the second surface; and (7) respectively forming a conductive wire on the first and second conductive layers. The light-emitting element of MOS semiconductor manufactured by the abovementioned steps is characterized in the emission of long wavelength.

    摘要翻译： 提供了具有IV族异质结的发光元件的制造方法。 该方法至少包括以下步骤：（1）提供具有第一和第二表面的硅衬底; （2）在第一表面上形成锗层; （3）在锗层上形成盖层; （4）在盖层上形成氧化层; （5）在氧化层上形成第一导电层; （6）在所述第二表面上形成第二导电层; 和（7）分别在第一和第二导电层上形成导线。 通过上述步骤制造的MOS半导体的发光元件的特征在于长波长的发射。

    NARROW CHANNEL WIDTH EFFECT MODIFICATION IN A SHALLOW TRENCH ISOLATION DEVICE
    5.
    发明申请
    NARROW CHANNEL WIDTH EFFECT MODIFICATION IN A SHALLOW TRENCH ISOLATION DEVICE 有权
    窄路径隔离装置中的窄频道宽度效应修正

    公开(公告)号：US20100323494A1

    公开(公告)日：2010-12-23

    申请号：US12486515

    申请日：2009-06-17

    申请人： Ming-Han Liao ,  Tze-Liang Lee

    发明人： Ming-Han Liao ,  Tze-Liang Lee

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76237

    摘要： A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

    摘要翻译： 提供一种制造半导体结构的方法。 该方法包括在半导体衬底上形成硬掩模图案，其中硬掩模图案覆盖有源区; 在由所述硬掩模图案限定的开口内在所述半导体衬底中形成沟槽; 用电介质材料填充沟槽，导致沟槽隔离特征; 使用所述硬掩模图案对所述沟槽隔离特征进行离子注入以保护所述半导体衬底的有源区; 并且在执行离子注入之后去除硬掩模图案。

    Isolation Region Implant and Structure
    6.
    发明申请
    Isolation Region Implant and Structure 审中-公开
    隔离区植物和结构

    公开(公告)号：US20100193879A1

    公开(公告)日：2010-08-05

    申请号：US12617515

    申请日：2009-11-12

    申请人： Ming-Han Liao ,  Tze-Liang Lee

    发明人： Ming-Han Liao ,  Tze-Liang Lee

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/76224 ,  H01L21/26586 ,  H01L29/66537 ,  H01L29/7833

    摘要： A method and structure for modulating the threshold voltage of transistor is provided. An opening for an isolation region is formed within a substrate using a masking layer. The masking layer is then pulled back from the opening, and dopants are implanted into the substrate through the exposed surface of the substrate and the sidewalls of the opening. This implantation can be tailored to modulate the threshold voltage of transistors with smaller gate widths without modulating the threshold voltage of other transistors with larger gate widths.

    摘要翻译： 提供了一种用于调制晶体管的阈值电压的方法和结构。 使用掩模层在衬底内形成用于隔离区的开口。 然后将掩模层从开口拉回，并且通过基板的暴露表面和开口的侧壁将掺杂剂注入到基板中。 可以调整这种注入以调制具有较小栅极宽度的晶体管的阈值电压，而不调制具有较大栅极宽度的其它晶体管的阈值电压。