摘要:
A target interface system for flexibly routing and timing communication signals exchanged between selected components of a communication system and methods for manufacturing and using same. Under the control of a host system, the target interface system samples an output data signal provided by the host system and includes a reconfigurable datapath for flexibly routing the sampled data signal to a selected target I/O pin of the target interface system. The selected target I/O pin provides the sampled data signal as an outgoing target data signal to a target system and likewise receives an incoming target data signal from the target system. Upon sampling the incoming target data signal, the target interface system flexibly routes the sampled data signal to the host system as an input data signal. The target interface system thereby facilitates exchanges of communication signals between the host system and the target system.
摘要:
A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.
摘要:
A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. Being reconfigurable to support an extensive range of conventional input/output technologies, the target interface system downloads a selected image associated with a desired input/output technology prior to runtime. The selected image identifies an appropriate output driver supply voltage, and any auxiliary voltages are controlled as functions of the output driver supply voltage to limit voltage inconsistencies. Defaulting each voltage to its least dangerous state when unprogrammed, the target interface system subsequently monitors the voltages, disabling the input/output connections if a problem is detected. The target interface system likewise detects when a selected system component is absent, unpowered, and/or wrongly powered and provides contention detection. Thereby, the target interface system can facilitate communication among the system components while inhibiting damage to the target interface system and/or the system components.
摘要:
A signal conversion system for interfacing selected components of a communication system and methods for manufacturing and using same. The signal conversion system converts selected logic signals from one system component into a pair of differential logic signals and provides the pair of differential logic signals to a second system component, resolving any logical and/or temporal artifacts. While one or more of the selected logic signals change signal state, the signal conversion system maintains the pair of differential logic signals in a first valid combined signal state until the signal state of the selected logic signals corresponds to a second valid combined signal state for the pair of differential logic signals. The signal verification system then updates the pair of differential logic signals to have the second valid combined signal state. The system components thereby can communicate, exchanging differential communication signals while maintaining duty cycle and avoiding signaling glitches.
摘要:
A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.
摘要:
A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.
摘要:
The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.
摘要:
An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.
摘要:
An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.
摘要:
An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.