公开(公告)号：US07208836B2

公开(公告)日：2007-04-24

申请号：US10648886

申请日：2003-08-26

Applicant: Monte Manning

Inventor： Monte Manning

IPC: H01L23/48 ,  H01L23/58

CPC classification number: H01L21/76838 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a first insulating material layer over the first conductive layer; d) etching through the first insulating layer and the first conductive layer to the substrate to both form a plurality of first conductive lines from the first conductive layer and provide a plurality of grooves between the first lines, the first lines being capped by first insulating layer material, the first lines having respective sidewalls; e) electrically insulating the first line sidewalls; and f) after insulating the sidewalls, providing the grooves with a second conductive material to form a plurality of second lines within the grooves which alternate with the first lines. Integrated circuitry formed according to the method, and other methods, is also disclosed.

Abstract translation: 形成多根导线的半导体加工方法包括：a）提供基板; b）在衬底上提供第一导电材料层; c）在所述第一导电层上设置第一绝缘材料层; d）通过第一绝缘层和第一导电层蚀刻到衬底，以从第一导电层形成多个第一导电线，并在第一线之间提供多个沟槽，第一线被第一绝缘层 材料，第一线具有各自的侧壁; e）电绝缘第一线侧壁; 以及f）在绝缘侧壁之后，为所述凹槽提供第二导电材料以在所述凹槽内形成与所述第一线交替的多个第二线。 还公开了根据该方法形成的集成电路和其它方法。

公开(公告)号：US20050156243A1

公开(公告)日：2005-07-21

申请号：US11038601

申请日：2005-01-18

Applicant: Monte Manning

Inventor： Monte Manning

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/00 ,  H01L27/12 ,  H01L29/94

CPC classification number: H01L29/66666 ,  H01L29/6675 ,  H01L29/7827

Abstract: A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel region occurring by any separate masking layer. A method includes, a) providing a substrate having a node to which electrical connection is to be made; b) providing a first electrically insulative dielectric layer over the substrate; c) providing an electrically conductive gate layer over the first dielectric layer; d) providing a second electrically insulative dielectric layer over the electrically conductive gate layer; e) providing a contact opening through the second dielectric layer, the electrically conductive gate layer and the first dielectric layer; the contact opening defining projecting sidewalls; f) providing a gate dielectric layer within the contact opening laterally inward of the projecting sidewalls; g) providing a layer of semiconductive material over the second dielectric layer and within the contact opening against the gate dielectric layer and in electrical communication with the node; the semiconductive material within the contact opening defining an elongated and outwardly extending channel region the electrical conductance of which can be modulated by means of the adjacent electrically conductive gate and gate dielectric layers; and h) conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region of a thin film transistor. Thin film transistor constructions are also disclosed.

Abstract translation: 提供了一种在衬底上形成薄膜晶体管的方法，其中至少一个源极区或漏极区是导电掺杂的，同时防止沟道区的导电掺杂，而不会对通过任何单独的掩模层发生的沟道区进行掩蔽。 一种方法包括：a）提供具有要与其进行电连接的节点的基板; b）在衬底上提供第一电绝缘介质层; c）在所述第一介电层上提供导电栅极层; d）在所述导电栅极层上方提供第二电绝缘介质层; e）提供通过第二介电层，导电栅极层和第一介电层的接触开口; 所述接触开口限定突出的侧壁; f）在所述接触开口内在所述突出侧壁的横向内侧设置栅极电介质层; g）在所述第二电介质层上方并且在所述接触开口内提供半导体材料层以抵靠所述栅极介电层并与所述节点电连通; 接触开口内的半导体材料限定了可以通过相邻的导电栅极和栅极电介质层调节电导的细长且向外延伸的沟道区域; 以及h）导电地掺杂位于所述接触开口外侧的所述半导体材料层，以形成薄膜晶体管的源极区域或漏极区域中的一个。 还公开了薄膜晶体管结构。

公开(公告)号：US20050145850A1

公开(公告)日：2005-07-07

申请号：US11063688

申请日：2005-02-22

Applicant: Charles Dennison ,  Monte Manning

Inventor： Charles Dennison ,  Monte Manning

IPC: H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L29/04 ,  H01L23/48 ,  H01L29/10 ,  H01L29/15

CPC classification number: H01L29/6675 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78648 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract translation: 电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。 这样可用于制造薄膜晶体管和其他电路。

公开(公告)号：US06689649B2

公开(公告)日：2004-02-10

申请号：US09884292

申请日：2001-06-18

Applicant: Charles H. Dennison ,  Monte Manning

Inventor： Charles H. Dennison ,  Monte Manning

IPC: H01L2100

CPC classification number: H01L29/6675 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78648 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract translation: 电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。 这样可用于制造薄膜晶体管和其他电路。

公开(公告)号：US06589821B2

公开(公告)日：2003-07-08

申请号：US08996325

申请日：1997-12-22

Applicant: Monte Manning

Inventor： Monte Manning

IPC: H01L2100

CPC classification number: H01L29/66666 ,  H01L29/6675 ,  H01L29/7827

Abstract: A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel region occurring by any separate masking layer. A method includes, a) providing a substrate having a node to which electrical connection is to be made; b) providing a first electrically insulative dielectric layer over the substrate; c) providing an electrically conductive gate layer over the first dielectric layer; d) providing a second electrically insulative dielectric layer over the electrically conductive gate layer; e) providing a contact opening through the second dielectric layer, the electrically conductive gate layer and the first dielectric layer; the contact opening defining projecting sidewalls; f) providing a gate dielectric layer within the contact opening laterally inward of the projecting sidewalls; g) providing a layer of semiconductive material over the second dielectric layer and within the contact opening against the gate dielectric layer and in electrical communication with the node; the semiconductive material within the contact opening defining an elongated and outwardly extending channel region the electrical conductance of which can be modulated by means of the adjacent electrically conductive gate and gate dielectric layers; and h) conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region of a thin film transistor. Thin film transistor construction are also disclosed.

Abstract translation: 提供了一种在衬底上形成薄膜晶体管的方法，其中至少一个源极区或漏极区是导电掺杂的，同时防止沟道区的导电掺杂，而不会对通过任何单独的掩模层发生的沟道区进行掩蔽。 一种方法包括：a）提供具有要与其进行电连接的节点的基板; b）在衬底上提供第一电绝缘介质层; c）在所述第一介电层上提供导电栅极层; d）在所述导电栅极层上方提供第二电绝缘介质层; e）提供通过第二介电层，导电栅极层和第一介电层的接触开口; 所述接触开口限定突出的侧壁; f）在所述接触开口内在所述突出侧壁的横向内侧设置栅极电介质层; g）在所述第二电介质层上方并且在所述接触开口内提供半导体材料层以抵靠所述栅极介电层并与所述节点电连通; 接触开口内的半导体材料限定了可以通过相邻的导电栅极和栅极电介质层调节电导的细长且向外延伸的沟道区域; 以及h）导电地掺杂位于所述接触开口外侧的所述半导体材料层，以形成薄膜晶体管的源极区域或漏极区域中的一个。 还公开了薄膜晶体管结构。

公开(公告)号：US06445044B1

公开(公告)日：2002-09-03

申请号：US09126182

申请日：1998-07-30

Applicant: Monte Manning

Inventor： Monte Manning

IPC: H01L2978

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

公开(公告)号：US06351038B1

公开(公告)日：2002-02-26

申请号：US09422036

申请日：1999-10-20

Applicant: Monte Manning

Inventor： Monte Manning

IPC: H01L2348

CPC classification number: H01L21/76895

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion. The outer portion has a terminus and the inner portion extends laterally away from the outer portion terminus and generally toward the node location. The inner portion is in electrical communication with the node location.

Abstract translation: 在导电线路和节点位置之间进行电连接的半导体处理方法包括：a）在衬底上形成导电线，所述衬底具有向外暴露的含硅节点位置，电连接将被制成， 所述内部部分从所述外部部分向外横向延伸并且具有外露部分，所述内部部分具有邻近所述节点位置的终端，以及b）将所述延伸内部部分与所述节点电连接 位置。 还描述了集成电路。 集成电路包括半导体衬底，衬底上的节点位置以及衬底上与节点位置电连通的导电线。 导线包括外部部分和内部部分。 外部具有末端，并且内部部分横向延伸远离外部部分终端并且大致朝节点位置延伸。 内部部分与节点位置电连通。

公开(公告)号：US06319800B1

公开(公告)日：2001-11-20

申请号：US09638970

申请日：2000-08-15

Applicant: Monte Manning

Inventor： Monte Manning

IPC: H01L2122

CPC classification number: H01L27/11

Abstract: A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activate the access transistors which couple the memory cell to complementary bit lines. The memory cells, as viewed in a plan view, have the single word line and gates of the pulldown transistors fabricated in parallel.

Abstract translation: 描述了具有交叉耦合下拉晶体管和双存取晶体管的静态存储单元。 存储单元被制造成使得通过两个下拉晶体管形成平衡电流路径。 单个字线用于激活将存储器单元耦合到互补位线的存取晶体管。 如平面图所示，存储单元具有并行制造的下拉晶体管的单个字线和栅极。

公开(公告)号：US06306696B1

公开(公告)日：2001-10-23

申请号：US09025214

申请日：1998-02-18

Applicant: Charles H. Dennison ,  Monte Manning

Inventor： Charles H. Dennison ,  Monte Manning

IPC: H01L2100

CPC classification number: H01L29/6675 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78648 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically a etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract translation: 电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性地蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。 这样可用于制造薄膜晶体管和其他电路。

公开(公告)号：US06177346B1

公开(公告)日：2001-01-23

申请号：US09154546

申请日：1998-09-16

Applicant: Monte Manning

Inventor： Monte Manning

IPC: H01L2144

CPC classification number: H01L29/78612 ,  H01L23/485 ,  H01L29/41733 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a field effect transistor includes, a) providing a silicon substrate having impurity doping of a first conductivity type; b) providing source and drain diffusion regions of a second conductivity type within the silicon substrate, the source region and the drain region being spaced from one another to define a channel region therebetween within the silicon substrate; c) providing a gate relative to the silicon substrate operatively adjacent the channel region; and d) providing respective ohmic electrical contacts to the source region and the drain region, the electrical contact to the source region comprising a substrate leaking junction, the electrical connection to the drain region not comprising a substrate leaking junction. A field effect transistor is also disclosed.

Abstract translation: 形成场效应晶体管的方法包括：a）提供具有第一导电类型的杂质掺杂的硅衬底; b）在硅衬底内提供第二导电类型的源极和漏极扩散区域，所述源极区域和漏极区域彼此间隔开以在所述硅衬底内限定沟槽区域; c）相对于沟槽区域可操作地提供相对于硅衬底的栅极; 以及d）向所述源极区域和所述漏极区域提供相应的欧姆电触点，所述源极区域的电接触包括基底泄漏接头，到所述漏极区域的电连接不包括基底泄漏接头。 还公开了场效应晶体管。