公开(公告)号：US06614376B2

公开(公告)日：2003-09-02

申请号：US09990251

申请日：2001-11-21

Applicant: Yukio Tanaka ,  Munehiko Azami

Inventor： Yukio Tanaka ,  Munehiko Azami

IPC: H03M166

CPC classification number: H03M1/68 ,  H03M1/765 ,  H03M1/804

Abstract: A D/A converter circuit capable of handling a high bit number digital signal, having good linearity, and having a small occupied surface area is provided. The D/A converter circuit has n−m+1 capacitors (where m is a natural number, and smaller than n), and the supply and discharge of electric charge to one of the capacitors from among the n−m+1 capacitors are controlled by the lower m bits of a digital video signal. The supply and discharge of electric charge to the remaining n−m capacitors, from among the n−m+1 capacitors, are controlled by the upper n−m bits, from among the n bits, of the digital video signal.