公开(公告)号：US06812879B2

公开(公告)日：2004-11-02

申请号：US10460199

申请日：2003-06-13

申请人： Naoko Suwa ,  Yasuo Morimoto

发明人： Naoko Suwa ,  Yasuo Morimoto

IPC分类号： H03M166

CPC分类号： H03M1/005 ,  H03M1/662 ,  H03M1/685 ,  H03M1/747

摘要： A D/A converter can convert M digital signals to M analog signals simultaneously in accordance with used conditions, where M is an integer greater than one. The D/A converter includes a current matrix cell, N weighting cells, and a control circuit, where N is an integer equal to or greater than M. The control circuit divides the current matrix cell in accordance with the number M of digital signals to be D/A converted, and supplies the current matrix cell after the division with specified bits constituting the M digital signals. The control circuit also supplies only the M weighting cells out of the N weighting cells with the remaining bits of the individual M digital signals. The M analog signals are obtained by adding the M currents the current matrix cell produces and the M currents the M weighting cells produce.

摘要翻译： D / A转换器可以根据使用的条件同时将M个数字信号转换为M个模拟信号，其中M是大于1的整数。 D / A转换器包括当前矩阵单元，N个加权单元和控制电路，其中N是等于或大于M的整数。控制电路根据数字信号的数量M将当前矩阵单元划分为 进行D / A转换，并将分配后的当前矩阵单元提供给构成M个数字信号的指定位。 控制电路还仅向N个加权单元中的M个加权单元提供各个M个数字信号的剩余位。 M模拟信号通过将当前矩阵单元产生的M个电流和M个加权单元产生的M个电流相加来获得。

公开(公告)号：US6060918A

公开(公告)日：2000-05-09

申请号：US281168

申请日：1994-07-27

申请人： Kazuhito Tsuchida ,  Naoko Suwa

发明人： Kazuhito Tsuchida ,  Naoko Suwa

IPC分类号： H01L27/092 ,  G05F3/20 ,  G05F3/24 ,  H01L21/8238 ,  H03K17/22 ,  G05F1/10

CPC分类号： H03K17/223 ,  G05F3/205

摘要： There is disclosed a start-up circuit (3a) wherein a plurality of NMOSs (Q8 to Q10) are connected in series between the drain of a PMOS (Q1) and a ground potential point (2) and connected at their gate to a power-supply potential point (1), and wherein a voltage drop at the NMOSs (Q8 to Q10) generates a gate potential of a PMOS (Q2) for supplying current to a bias supply circuit (4). By using the voltage drop of the NMOSs (Q8 to Q10) having a small area, the start-up circuit including a CMOS is reduced in layout area.

摘要翻译： 公开了一种启动电路（3a），其中多个NMOS（Q8至Q10）串联连接在PMOS（Q1）的漏极和地电位点（2）之间，并在其栅极处连接到电源 （1），并且其中NMOS（Q8至Q10）处的电压降产生用于向偏置电源电路（4）提供电流的PMOS（Q2）的栅极电位。 通过使用具有小面积的NMOS（Q8至Q10）的电压降，包括CMOS的启动电路在布局区域中减小。

公开(公告)号：US06707333B2

公开(公告)日：2004-03-16

申请号：US10234479

申请日：2002-09-05

申请人： Osamu Matsumoto ,  Masao Ito ,  Naoko Suwa

发明人： Osamu Matsumoto ,  Masao Ito ,  Naoko Suwa

IPC分类号： H03K301

CPC分类号： G05F3/205

摘要： A Veff detector circuit generates input voltages VEP, VEN on the basis of a bias voltage which is fed back so that the difference between these input voltages may be a saturation voltage Veff, and a four-input operational amplifier means receives the input voltages VEP, VEN generated by the Veff detector circuit and generates the bias voltage VB by using reference voltages VERP, VERN which are externally inputted.

摘要翻译： Veff检测器电路基于反馈的偏置电压产生输入电压VEP，VEN，使得这些输入电压之间的差可以是饱和电压Veff，并且四输入运算放大器装置接收输入电压VEP， VEN由Veff检测器电路产生并通过使用外部输入的参考电压VERP，VERN产生偏置电压VB。