公开(公告)号：US07453286B1

公开(公告)日：2008-11-18

申请号：US11788657

申请日：2007-04-19

Applicant: Jorge Ernesto Carrillo ,  Raj Kumar Nagarajan ,  James M. Pangburn ,  Navaneethan Sundaramoorthy

Inventor： Jorge Ernesto Carrillo ,  Raj Kumar Nagarajan ,  James M. Pangburn ,  Navaneethan Sundaramoorthy

IPC: G06F7/38 ,  H03K19/173

CPC classification number: G06F7/026

Abstract: A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output associated with the first comparison function to select an output of the comparator. A device having programmable logic comprising a comparator is also described.

Abstract translation: 描述了在具有可编程逻辑的设备中实现比较器的方法。 该方法包括在第一查找表中实现第一比较功能; 在第二查找表中实现第二比较功能; 以及使用与第一比较功能相关联的输出来选择比较器的输出。 还描述了具有包括比较器的可编程逻辑的装置。

公开(公告)号：US07840781B1

公开(公告)日：2010-11-23

申请号：US11732721

申请日：2007-04-04

Applicant: Sivakumar Velusamy ,  Navaneethan Sundaramoorthy ,  Raj Kumar Nagarajan ,  Satish R. Ganesan

Inventor： Sivakumar Velusamy ,  Navaneethan Sundaramoorthy ,  Raj Kumar Nagarajan ,  Satish R. Ganesan

IPC: G06F13/00

CPC classification number: G06F11/3636 ,  G06F11/348 ,  G06F11/364 ,  G06F11/3648

Abstract: Various approaches for profiling a target system are described. In one approach, a uni-directional, point-to-point bus has a single input port and a single output port. A target processor has a trace port coupled to the input port of the bus and is configured to execute a plurality of instructions one or more times. The target processor provides state data at the trace port and to the input port of the bus. A profile circuit arrangement is coupled to the output port of the first bus, and a memory is coupled to the profile circuit arrangement. The profile circuit arrangement is configured to read data from the output port of the first bus and write the data to the memory.

Abstract translation: 描述用于分析目标系统的各种方法。 在一种方法中，单向点对点总线具有单个输入端口和单个输出端口。 目标处理器具有耦合到总线的输入端口的跟踪端口，并且被配置为执行多个指令一次或多次。 目标处理器在跟踪端口和总线的输入端口提供状态数据。 简档电路布置被耦合到第一总线的输出端口，并且存储器耦合到简档电路装置。 简档电路装置被配置为从第一总线的输出端口读取数据并将数据写入存储器。

公开(公告)号：US07490227B1

公开(公告)日：2009-02-10

申请号：US10930437

申请日：2004-08-31

Applicant: Goran Bilski ,  Jorge Ernesto Carrillo ,  Usha Prabhu ,  Navaneethan Sundaramoorthy

Inventor： Goran Bilski ,  Jorge Ernesto Carrillo ,  Usha Prabhu ,  Navaneethan Sundaramoorthy

IPC: G06F11/25

CPC classification number: G06F11/3476

Abstract: A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.

Abstract translation: 在处理器中重建指令和数据迹线的方法可以包括以与顺序程序计数器（PC）值相对应的顺序从可执行程序获取指令的步骤，从获取的指令获取目的地寄存器并且更新目的地寄存器 具有来自与PC值相对应的收集的目的地寄存器的值的数据结构。 可以重复上述步骤，直到获得所有期望的PC值和目标值。

公开(公告)号：US08447957B1

公开(公告)日：2013-05-21

申请号：US11598990

申请日：2006-11-14

Applicant: Jorge Ernesto Carrillo ,  Navaneethan Sundaramoorthy ,  Sivakumar Velusamy ,  Ralph D. Wittig ,  Vasanth Asokan

Inventor： Jorge Ernesto Carrillo ,  Navaneethan Sundaramoorthy ,  Sivakumar Velusamy ,  Ralph D. Wittig ,  Vasanth Asokan

IPC: G06F9/345

CPC classification number: G06F13/1684 ,  G06F9/3455 ,  G06F9/3881

Abstract: A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.

Abstract translation: 一种新颖的协处理器接口，无需遍历主处理器即可提供存储器访问，以及操作该处理器的方法。 系统包括总线，处理器电路，存储器电路，多通道存储器控制器和至少一个协处理器。 处理器电路耦合到总线，多通道存储器控制器耦合在总线和存储器电路之间，并且协处理器耦合到处理器电路和多通道存储器控制器两者。 该电路装置为协处理器和存储器电路之间的数据访问提供了专用的高速通道，而不用遍历处理器电路或总线。 因此，可以支持非标准（例如非顺序）数据传输协议。 在一些实施例中，系统在可编程逻辑器件（PLD）中实现。 处理器电路可以是例如包括在PLD中作为硬编码逻辑的微处理器，或者可以使用PLD的可编程逻辑元件来实现。