公开(公告)号：US08447957B1

公开(公告)日：2013-05-21

申请号：US11598990

申请日：2006-11-14

Applicant: Jorge Ernesto Carrillo ,  Navaneethan Sundaramoorthy ,  Sivakumar Velusamy ,  Ralph D. Wittig ,  Vasanth Asokan

Inventor： Jorge Ernesto Carrillo ,  Navaneethan Sundaramoorthy ,  Sivakumar Velusamy ,  Ralph D. Wittig ,  Vasanth Asokan

IPC: G06F9/345

CPC classification number: G06F13/1684 ,  G06F9/3455 ,  G06F9/3881

Abstract: A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.

Abstract translation: 一种新颖的协处理器接口，无需遍历主处理器即可提供存储器访问，以及操作该处理器的方法。 系统包括总线，处理器电路，存储器电路，多通道存储器控制器和至少一个协处理器。 处理器电路耦合到总线，多通道存储器控制器耦合在总线和存储器电路之间，并且协处理器耦合到处理器电路和多通道存储器控制器两者。 该电路装置为协处理器和存储器电路之间的数据访问提供了专用的高速通道，而不用遍历处理器电路或总线。 因此，可以支持非标准（例如非顺序）数据传输协议。 在一些实施例中，系统在可编程逻辑器件（PLD）中实现。 处理器电路可以是例如包括在PLD中作为硬编码逻辑的微处理器，或者可以使用PLD的可编程逻辑元件来实现。

公开(公告)号：US07840781B1

公开(公告)日：2010-11-23

申请号：US11732721

申请日：2007-04-04

Applicant: Sivakumar Velusamy ,  Navaneethan Sundaramoorthy ,  Raj Kumar Nagarajan ,  Satish R. Ganesan

Inventor： Sivakumar Velusamy ,  Navaneethan Sundaramoorthy ,  Raj Kumar Nagarajan ,  Satish R. Ganesan

IPC: G06F13/00

CPC classification number: G06F11/3636 ,  G06F11/348 ,  G06F11/364 ,  G06F11/3648

Abstract: Various approaches for profiling a target system are described. In one approach, a uni-directional, point-to-point bus has a single input port and a single output port. A target processor has a trace port coupled to the input port of the bus and is configured to execute a plurality of instructions one or more times. The target processor provides state data at the trace port and to the input port of the bus. A profile circuit arrangement is coupled to the output port of the first bus, and a memory is coupled to the profile circuit arrangement. The profile circuit arrangement is configured to read data from the output port of the first bus and write the data to the memory.

Abstract translation: 描述用于分析目标系统的各种方法。 在一种方法中，单向点对点总线具有单个输入端口和单个输出端口。 目标处理器具有耦合到总线的输入端口的跟踪端口，并且被配置为执行多个指令一次或多次。 目标处理器在跟踪端口和总线的输入端口提供状态数据。 简档电路布置被耦合到第一总线的输出端口，并且存储器耦合到简档电路装置。 简档电路装置被配置为从第一总线的输出端口读取数据并将数据写入存储器。

公开(公告)号：US07606694B1

公开(公告)日：2009-10-20

申请号：US11389348

申请日：2006-03-24

Applicant: Jorge Ernesto Carrillo ,  Satish R. Ganesan ,  Amit Kasat ,  Sivakumar Velusamy

Inventor： Jorge Ernesto Carrillo ,  Satish R. Ganesan ,  Amit Kasat ,  Sivakumar Velusamy

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.

Abstract translation: 用于执行电路设计的循环精确模拟的系统可以包括多个周期精确模型，其中每个周期精确模型是硬件功能的软件对象表示，以及调度器，被配置为在确定的时钟周期边界执行每个周期精确模型 在模拟会话期间。

公开(公告)号：US06938146B2

公开(公告)日：2005-08-30

申请号：US10324512

申请日：2002-12-19

Applicant: Hazim Shafi ,  Sivakumar Velusamy

Inventor： Hazim Shafi ,  Sivakumar Velusamy

IPC: G06F1/32 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/0862 ,  G06F2212/1028 ,  G06F2212/6022 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for improving memory performance and decreasing memory power requirements is described. To accomplish the improvements, a prefetch buffer is added to a memory controller with accompanying prefetch logic. The memory controller first attempts to satisfy memory requests from the prefetch buffer allowing the main memory to stay in a reduced power state until accessing it is required. If the memory controller is unable to satisfy a memory request from the prefetch buffer, the main memory is changed to an active power state and the prefetch logic is invoked. The prefetch logic loads the requested memory, returns the request memory to the requester, and loads memory likely to be requested in the near future into the prefetch buffer. Concurrent with the execution of the prefetch logic, the memory controller returns the requested data. Following the retrieval from main memory, the memory controller may place the main memory into a reduced power state immediately, or after a selected interval, based upon the likelihood of a subsequent memory request miss.

Abstract translation: 描述了用于提高存储器性能和降低存储器功率需求的系统和方法。 为了完成这些改进，预取缓冲区被附加到带有预取逻辑的存储器控​​制器中。 存储器控制器首先尝试满足来自预取缓冲器的存储器请求，允许主存储器保持在降低的功率状态，直到需要访问它。 如果存储器控制器不能满足来自预取缓冲器的存储器请求，则将主存储器改变为有功功率状态，并且调用预取逻辑。 预取逻辑加载请求的存储器，将请求存储器返回给请求者，并将可能在不久的将来请求的内存加载到预取缓冲器中。 与预取逻辑的执行同时，存储器控制器返回所请求的数据。 在从主存储器检索之后，存储器控制器可以基于随后的存储器请求丢失的可能性立即将主存储器置于降低功率状态，或者在选定间隔之后。