公开(公告)号：US07176113B1

公开(公告)日：2007-02-13

申请号：US10862636

申请日：2004-06-07

申请人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

发明人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

IPC分类号： H01L21/425

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.

摘要翻译： 本发明涉及在形成存储器件中实施轻掺杂通道（LDC）植入物以改善Vt滚降等。 轻掺杂通道有助于保持通道完整性，使得阈值电压（Vt）可以保持在相对稳定的水平，从而减轻Vt滚降。 LDC还有助于减少掩埋位线宽度，从而使位线更靠近在一起。 因此，可以在相同或更小的区域内形成或“包装”更多的装置。

公开(公告)号：US07011998B1

公开(公告)日：2006-03-14

申请号：US10756573

申请日：2004-01-12

申请人： Dong-Hyuk Ju ,  Nga-Ching (Alan) Wong

发明人： Dong-Hyuk Ju ,  Nga-Ching (Alan) Wong

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7836 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention is a high voltage transistor formation method and system that includes a varying or gradient concentration lightly doped drain and source implant region. The lightly doped drain (LDD) implant region has gradient concentration characteristics that provide a higher concentration under a source and drain and lower concentration close to a surface source drain channel formation under a gate. A lightly doped drain tilt implant process is utilized to form a component area (e.g., a transistor source and/or drain area) with gradient doping profiles. The varying concentration profile provides a smooth electrical characteristic transformation between regions that reduces the probability of hot electron generation otherwise associated with electrical fields that cross abrupt changes between different conductivity orientation regions. The higher concentration of the light dopants at the bottom of the source and drain regions also helps reduce the probability of deep junction breakdown.

摘要翻译： 本发明是一种高压晶体管形成方法和系统，其包括变化或梯度浓度的轻掺杂漏极和源极注入区域。 轻掺杂漏极（LDD）注入区域具有梯度浓度特性，其在靠近栅极处的表面源极沟道形成的源极和漏极以及较低的浓度下提供更高的浓度。 利用轻掺杂的漏极倾斜注入工艺来形成具有梯度掺杂分布的分量区域（例如，晶体管源极和/或漏极区域）。 变化的浓度分布提供了区域之间的平滑电特性转换，其减少热电子产生的可能性，否则与在不同导电取向区域之间交叉突变的电场相关。 在源极和漏极区域底部的较高浓度的光掺杂剂也有助于降低深结击穿的可能性。

公开(公告)号：US06958272B2

公开(公告)日：2005-10-25

申请号：US10755740

申请日：2004-01-12

申请人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

发明人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。 抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。 然后执行位线注入以在衬底内建立掩埋位线。 然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。 在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。 口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。 因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。