公开(公告)号：US08999061B2

公开(公告)日：2015-04-07

申请号：US13318950

申请日：2010-05-07

申请人： Masayuki Ishibashi ,  Tomonori Miura

发明人： Masayuki Ishibashi ,  Tomonori Miura

IPC分类号： C30B25/02 ,  H01L21/306 ,  C30B33/08 ,  C30B29/06 ,  C30B33/00 ,  H01L21/02

CPC分类号： H01L21/30625 ,  C30B25/02 ,  C30B29/06 ,  C30B33/00 ,  C30B33/08 ,  H01L21/02381 ,  H01L21/02658 ,  Y10S438/959

摘要： The method for producing a silicon epitaxial wafer according to the present invention has: a growth step G at which an epitaxial layer is grown on a silicon single crystal substrate; a first polishing step E at which, before the growth step G, both main surfaces of the silicon single crystal substrate are subjected to rough polishing simultaneously; and a second polishing step H at which, after the growth step G, the both main surfaces of the silicon single crystal substrate are subjected to finish polishing simultaneously.

摘要翻译： 根据本发明的硅外延晶片的制造方法具有：在硅单晶基板上生长外延层的生长工序G; 在生长步骤G之前，同时对硅单晶衬底的两个主表面进行粗抛光的第一抛光步骤E; 以及在生长步骤G之后同时对硅单晶基板的两个主表面进行精加工抛光的第二抛光步骤H.

公开(公告)号：US08187907B1

公开(公告)日：2012-05-29

申请号：US12775946

申请日：2010-05-07

申请人： Fred Newman

发明人： Fred Newman

IPC分类号： H01L21/00

CPC分类号： H01L31/06875 ,  H01L31/022425 ,  H01L31/0504 ,  Y02E10/544 ,  Y02P70/521 ,  Y10S438/959

摘要： A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.

摘要翻译： 一种通过提供第一基板来制造太阳能电池的方法; 在第一衬底上沉积形成包括顶部子电池和底部子电池的太阳能电池的半导体材料层序列; 在底部子电池上形成金属背接触; 在背面金属触点的表面上形成一组离散的间隔开的第一粘合元件; 使用所述接合元件在所述背面金属接触件的顶部附接替代基板; 以及去除所述第一衬底以暴露所述顶部子电池的表面。

公开(公告)号：US08062958B2

公开(公告)日：2011-11-22

申请号：US12416609

申请日：2009-04-01

申请人： Alan G. Wood ,  Ed A. Schrock ,  Ford B. Grigg

发明人： Alan G. Wood ,  Ed A. Schrock ,  Ford B. Grigg

IPC分类号： H01L21/30

CPC分类号： H01L21/3043 ,  H01L21/02035 ,  H01L21/3083 ,  Y10S438/959

摘要： Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

摘要翻译： 形成微电子器件晶片的方法包括在半导体晶片的有源侧制造多个半导体管芯，在半导体晶片上沉积掩模，去除掩模的中心部分和半导体晶片以及蚀刻。 半导体晶片具有外边缘和与活动侧间隔第一厚度的背面。 掩模沉积在半导体晶片的背面，并且具有与背面间隔开掩模厚度的面。 减薄部分具有与主动侧隔开比第一厚度小的第二厚度的薄化表面，并且减薄的表面被蚀刻。

公开(公告)号：US20110049679A1

公开(公告)日：2011-03-03

申请号：US12940733

申请日：2010-11-05

申请人： Keiji ISHIBASHI ,  Hidenori Mikami ,  Naoki Matsumoto

发明人： Keiji ISHIBASHI ,  Hidenori Mikami ,  Naoki Matsumoto

IPC分类号： H01L29/04 ,  H01L21/78

CPC分类号： H01L21/02021 ,  C30B29/403 ,  C30B33/00 ,  H01L24/32 ,  H01L33/0075 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/12042 ,  Y10S438/928 ,  Y10S438/959 ,  Y10S438/977 ,  H01L2924/00014 ,  H01L2924/00

摘要： A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 μm-10 μm thick edge process-induced degradation layer.

摘要翻译： 氮化物半导体晶片通过研磨晶片的底面进行平面加工，例如通过KOH去除底部工艺诱导的降解层，蚀刻底面，通过与100重量％-60重量％粘合的橡胶砂轮倒角， ＃3000-＃600金刚石颗粒和0重量％-40重量％的氧化物颗粒，研磨和抛光晶片的顶表面，蚀刻顶表面以消除顶部工艺诱导的降解层并保持0.5μm-10μm厚 边缘过程诱导的降解层。

公开(公告)号：US20100252915A1

公开(公告)日：2010-10-07

申请号：US12416609

申请日：2009-04-01

申请人： Alan G. Wood ,  Ed A. Schrock ,  Ford B. Grigg

发明人： Alan G. Wood ,  Ed A. Schrock ,  Ford B. Grigg

IPC分类号： H01L29/34 ,  H01L21/304

CPC分类号： H01L21/3043 ,  H01L21/02035 ,  H01L21/3083 ,  Y10S438/959

摘要： Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

摘要翻译： 形成微电子器件晶片的方法包括在半导体晶片的有源侧制造多个半导体管芯，在半导体晶片上沉积掩模，去除掩模的中心部分和半导体晶片以及蚀刻。 半导体晶片具有外边缘和与活动侧间隔第一厚度的背面。 掩模沉积在半导体晶片的背面，并且具有与背面间隔开掩模厚度的面。 减薄部分具有与主动侧隔开比第一厚度小的第二厚度的薄化表面，并且减薄的表面被蚀刻。

公开(公告)号：US07659207B2

公开(公告)日：2010-02-09

申请号：US11517620

申请日：2006-09-08

申请人： Reinhard Schauer ,  Thorsten Schneppensieper

发明人： Reinhard Schauer ,  Thorsten Schneppensieper

IPC分类号： H01L21/311

CPC分类号： C30B25/12 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  Y10S438/959

摘要： Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by placing a wafer on a susceptor, pretreating under a hydrogen atmosphere, in and then with addition of an etching medium, and coating epitaxially on a polished front side, wherein an etching treatment of the susceptor is effected after a specific number of epitaxial coatings, and the susceptor is then hydrophilized. Silicon wafer produced thereby have a maximum local flatness value SFQRmax of 0.01 μm to 0.035 μm relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm2 on the front side of the silicon wafer with an edge exclusion of 2 mm.

摘要翻译： 外延涂覆的硅晶片通过将晶片放置在基座上，在氢气气氛下预处理，然后加入蚀刻介质，并在抛光的正面上外延地涂覆在外延反应器中，其中蚀刻处理 感受器在特定数量的外延涂层之后进行，然后将基座亲水化。 所生产的硅晶片相对于硅晶片正面的尺寸为26×8mm 2的测量窗的区域格栅的部分区域的至少99％，具有0.01μm至0.035μm的最大局部平坦度SFQRmax，其具有 边缘排除2mm。

公开(公告)号：US07625821B2

公开(公告)日：2009-12-01

申请号：US11420591

申请日：2006-05-26

申请人： Kert L. Dolechek ,  Raymon F. Thompson

发明人： Kert L. Dolechek ,  Raymon F. Thompson

IPC分类号： H01L21/302

CPC分类号： H01L29/06 ,  H01L21/302 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/67126 ,  H01L21/68735 ,  Y10S438/959

摘要： The present invention provides system and apparatus for use in processing wafers. The new system and apparatus allows for the production of thinner wafers that at same time remain strong. As a result, the wafers produced by the present process are less susceptible to breaking. The unique system also offers an improved structure for handling thinned wafers and reduces the number of processing steps. This results in improved yields and improved process efficiency.

摘要翻译： 本发明提供了用于处理晶片的系统和装置。 新的系统和设备允许生产更薄的晶片，同时保持坚固。 结果，由本方法生产的晶片不易破裂。 独特的系统还提供了一种改进的处理薄化晶片的结构，并减少了处理步骤的数量。 这导致产量提高和工艺效率提高。

公开(公告)号：US20090230567A1

公开(公告)日：2009-09-17

申请号：US12046385

申请日：2008-03-11

申请人： James Yii Lee Kiong ,  Chong Hin Tan ,  Shivaram Sahadevan ,  Max Mah Boon Hooi ,  Tang Shiau Phing

发明人： James Yii Lee Kiong ,  Chong Hin Tan ,  Shivaram Sahadevan ,  Max Mah Boon Hooi ,  Tang Shiau Phing

IPC分类号： H01L23/31 ,  H01L21/58

CPC分类号： H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/97 ,  H01L2221/68386 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01078 ,  H01L2924/01084 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  Y10S438/959 ,  H01L2224/81 ,  H01L2924/00

摘要： A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.

摘要翻译： 公开了一种将模制的半导体封装研磨到期望的超薄厚度而不损坏封装的方法。 在将模制包装研磨至期望的包装厚度之前，可以通过施加保护带来包封形成在包装上的互连来保护包装在研磨期间产生的过大的机械应力。 这样，保护带在涉及模具材料以及模具的封装研磨期间为半导体封装提供支撑。 在后研磨包装中，研磨的模具表面可能暴露并与模具材料基本齐平。 然后可以移除保护胶带以准备用于与外部设备或PCB连接的后研磨包装。

公开(公告)号：US20090186563A1

公开(公告)日：2009-07-23

申请号：US12349870

申请日：2009-01-07

申请人： Aki Takahashi ,  Masaaki Nagashima

发明人： Aki Takahashi ,  Masaaki Nagashima

IPC分类号： B24B1/00

CPC分类号： B24B37/042 ,  B24B7/228 ,  Y10S438/959

摘要： In a wafer processing method, rough grinding using a first grinding stone is divided into first and second steps. In the first step, a wafer is processed into a concave shape at a first transfer rate with a reinforcing rib area slightly left. Thereafter, as primary rough grinding in the second step, the grinding stone is positioned slightly on the inner circumferential side and the wafer is further processed into the concave portion at a second transfer rate faster than the first transfer rate. Since the first transfer rate is suppressed to a rate not to cause a burst chipping, a burst chipping resulting from the second step fast in the processing rate to ensure productivity will occur at the stepped edge portion on the inside of the reinforcing rib area surface. Thus, the flatness of the reinforcing rib area can be ensured.

摘要翻译： 在晶片处理方法中，使用第一研磨石的粗磨被分为第一和第二步骤。 在第一步骤中，晶片以稍微离开的加强肋区域的第一传送速率被加工成凹形。 此后，作为第二工序中的一次粗磨，磨石稍微位于内周侧，并且以比第一传送速度快的第二传送速率进一步将晶片加工成凹部。 由于第一传送速率被抑制到不会引起突发片断的速率，因此在加强肋区域表面的内侧的阶梯状边缘部分处将发生由加工速度快的第二步骤产生的突发断裂以确保生产率。 因此，可以确保加强筋区域的平坦度。

公开(公告)号：US07554175B2

公开(公告)日：2009-06-30

申请号：US11686364

申请日：2007-03-15

申请人： Akihiro Hachigo

发明人： Akihiro Hachigo

IPC分类号： H01L21/304 ,  H01L21/302 ,  H01L27/06

CPC分类号： H01L21/02005 ,  C30B29/406 ,  C30B33/08 ,  H01L22/12 ,  H01L2924/0002 ,  Y10S438/959 ,  H01L2924/00

摘要： Fracture-resistant gallium nitride substrate, and methods of testing for and manufacturing such substrates are made available. A gallium nitride substrate (10) is provided with a front side (12) polished to a mirrorlike finish, a back side (14) on the substrate side that is the opposite of the front side (12). A damaged layer (16) whose thickness d is 30 μm or less is formed on the back side (14). Given that the strength of the front side (12) is I1 and the strength of the back side (14) is I2, then the ratio I2/I1 is 0.46 or more.

摘要翻译： 耐破坏氮化镓衬底，以及测试和制造这种衬底的方法是可用的。 氮化镓衬底（10）设置有抛光到镜面光洁度的前侧（12），在衬底侧的与前侧（12）相反的背面（14）。 在背面（14）上形成厚度d为30μm以下的受损层（16）。 假设前侧（12）的强度为I1，背面（14）的强度为I2，则I2 / I1的比值为0.46以上。