公开(公告)号：US06958272B2

公开(公告)日：2005-10-25

申请号：US10755740

申请日：2004-01-12

申请人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

发明人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。 抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。 然后执行位线注入以在衬底内建立掩埋位线。 然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。 在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。 口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。 因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

公开(公告)号：US20050153508A1

公开(公告)日：2005-07-14

申请号：US10755740

申请日：2004-01-12

申请人： Emmanuil Lingunis ,  Nga-Ching Wong ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Ashot Melik-Martirosian ,  Edward Runnion ,  Yi He

发明人： Emmanuil Lingunis ,  Nga-Ching Wong ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Ashot Melik-Martirosian ,  Edward Runnion ,  Yi He

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

公开(公告)号：US07176113B1

公开(公告)日：2007-02-13

申请号：US10862636

申请日：2004-06-07

申请人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

发明人： Nga-Ching Alan Wong ,  Weidong Qian ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Tazrien Kamal

IPC分类号： H01L21/425

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.

摘要翻译： 本发明涉及在形成存储器件中实施轻掺杂通道（LDC）植入物以改善Vt滚降等。 轻掺杂通道有助于保持通道完整性，使得阈值电压（Vt）可以保持在相对稳定的水平，从而减轻Vt滚降。 LDC还有助于减少掩埋位线宽度，从而使位线更靠近在一起。 因此，可以在相同或更小的区域内形成或“包装”更多的装置。

公开(公告)号：US6001713A

公开(公告)日：1999-12-14

申请号：US154074

申请日：1998-09-16

申请人： Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

发明人： Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

IPC分类号： H01L21/28 ,  H01L21/265

CPC分类号： H01L21/28273

摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.

摘要翻译： 提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。 该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。 所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。 这在浮动栅极内形成初始氮浓度分布。 然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。 浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。 因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。 已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。 与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。 因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

公开(公告)号：US06653189B1

公开(公告)日：2003-11-25

申请号：US09699711

申请日：2000-10-30

申请人： Sameer Haddad ,  Yue-song He ,  Timothy Thurgate ,  Chi Chang ,  Mark W. Randolph ,  Ngaching Wong

发明人： Sameer Haddad ,  Yue-song He ,  Timothy Thurgate ,  Chi Chang ,  Mark W. Randolph ,  Ngaching Wong

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L29/66833

摘要： One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.

摘要翻译： 本发明的一个方面涉及一种制造闪存单元的方法，包括以下步骤：在其上提供闪存单元; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 在衬底上形成MDD掩模，MDD掩模覆盖源极线并具有对应于漏极线的开口; 以及植入第二类型的介质剂量漏极注入，以在与所述闪存单元相邻的所述衬底中形成漏极区域。

公开(公告)号：US06934190B1

公开(公告)日：2005-08-23

申请号：US10863933

申请日：2004-06-09

申请人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

发明人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.

摘要翻译： 提供了包括具有一定范围值的编程的双位存储器件的操作方法。 本发明采用一系列斜坡源程序脉冲来迭代地执行采用热空穴注入的程序操作。 该范围与存储器件内的各个双位存储单元的通道长度有关。 为了编程一个特定的双位存储单元，负栅极编程电压被施加到其栅极，正的漏极电压被施加到其作用漏极，并且其衬底连接到地。 此外，斜坡源程序脉冲范围的斜坡源电压同时施加到双位存储单元的作用源。 然后执行验证操作，并且在验证失败时以递减的斜坡源电压重复编程。

公开(公告)号：US08482959B2

公开(公告)日：2013-07-09

申请号：US13324759

申请日：2011-12-13

申请人： Swaroop Kaza ,  Sameer Haddad

发明人： Swaroop Kaza ,  Sameer Haddad

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/79

摘要： A method of repairing a memory device is provided. If an erase process is unsuccessful, a repair process is performed. A programmed state of the memory device is determined, A subsequent erase process dependent on the programmed state is performed. Also, a method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.

摘要翻译： 提供了修复存储器件的方法。 如果擦除过程不成功，则执行修复过程。 确定存储器件的编程状态。执行取决于编程状态的后续擦除过程。 另外，提供了编程和擦除存储器件的方法。 存储器件包括第一和第二电极以及它们之间的开关层。 提供存储器件的第一导通电阻特性，通过将第一电压施加到与存储器件串联的晶体管的栅极来对存储器件进行编程。 可以通过将不同于第一电压的其他电压施加到晶体管的栅极来提供不同于第一导通电阻特性的存储器件的其他导通电阻特性。

公开(公告)号：US08232175B2

公开(公告)日：2012-07-31

申请号：US11521204

申请日：2006-09-14

申请人： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

发明人： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

IPC分类号： H01L21/20

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

摘要翻译： 制造存储器件的现有方法包括以下步骤：提供电介质层，在介电层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物 并且在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

公开(公告)号：US08084770B2

公开(公告)日：2011-12-27

申请号：US12313089

申请日：2008-11-17

申请人： Steven Avanzino ,  Suzette K. Pangrle ,  Manuj Rathor ,  An Chen ,  Sameer Haddad ,  Nicholas Tripsas ,  Matthew Buynoski

发明人： Steven Avanzino ,  Suzette K. Pangrle ,  Manuj Rathor ,  An Chen ,  Sameer Haddad ,  Nicholas Tripsas ,  Matthew Buynoski

IPC分类号： H01L29/10

CPC分类号： H01L22/32

摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

摘要翻译： 在本发明的电子测试结构中，提供了覆盖基板的导体。 电子器件覆盖导体的一部分，并且包括连接到导体的第一电极，第二电极和在第一和第二电极之间的绝缘层。 导体的一部分被暴露以便进入其中。

公开(公告)号：US07830015B2

公开(公告)日：2010-11-09

申请号：US11089708

申请日：2005-03-25

申请人： Zhida Lan ,  Sameer Haddad ,  Steven Avanzino

发明人： Zhida Lan ,  Sameer Haddad ,  Steven Avanzino

IPC分类号： H01L23/48

CPC分类号： G11C13/0009 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes and into which ions from the passive layer may be provided, and from which the ions may be provided into the passive layer. The active layer is made up of a base material and an impurity therein. The combined the material and impurity have a lower diffusion coefficient than the base material alone.

摘要翻译： 本存储器件包括第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层，并且可以提供来自被动层的离子，并且可以从其提供离子 进入被动层。 有源层由基材和杂质构成。 材料和杂质的组合具有比单独的基材更低的扩散系数。