Test and observe mode for embedded memory
    1.
    发明授权
    Test and observe mode for embedded memory 有权
    嵌入式内存的测试和观察模式

    公开(公告)号:US06535999B1

    公开(公告)日:2003-03-18

    申请号:US09352352

    申请日:1999-07-13

    IPC分类号: G01R3128

    摘要: A method and apparatus that tests and observes how an embedded DRAM is being accessed by a logic circuit controlling the DRAM is provided. The test and observe method and apparatus pipes the outputs of the logic, which is used as inputs to the embedded DRAM, to an observation device. The outputs of the logic device are then observed at the observation device to determine how the DRAM is being accessed. In addition, information concerning what data is being trapped and when may be output to the observation device to determine setup and hold times for the DRAM.

    摘要翻译: 提供一种测试和观察由控制DRAM的逻辑电路如何访问嵌入式DRAM的方法和装置。 测试和观察方法和装置将用作嵌入式DRAM的输入的逻辑的输出管道连接到观察装置。 然后在观察设备处观察逻辑设备的输出,以确定如何访问DRAM。 另外,关于什么数据被捕获和什么时候可以被输出到观察装置以确定DRAM的建立和保持时间的信息。

    TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES
    2.
    发明申请
    TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES 失效
    测试半导体器件中的保险丝配置

    公开(公告)号:US20110291693A1

    公开(公告)日:2011-12-01

    申请号:US13206434

    申请日:2011-08-09

    IPC分类号: G01R31/26

    摘要: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

    摘要翻译: 用于测试半导体器件的方法,系统和设备。 半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。 半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路,以及包括保险丝的熔丝电路,并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。 熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

    Testing fuse configurations in semiconductor devices
    3.
    发明授权
    Testing fuse configurations in semiconductor devices 失效
    测试半导体器件中的保险丝配置

    公开(公告)号:US08717052B2

    公开(公告)日:2014-05-06

    申请号:US13206434

    申请日:2011-08-09

    IPC分类号: G01R31/3187

    摘要: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

    摘要翻译: 用于测试半导体器件的方法,系统和设备。 半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。 半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路,以及包括保险丝的熔丝电路,并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。 熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

    Testing fuse configurations in semiconductor devices
    4.
    发明授权
    Testing fuse configurations in semiconductor devices 有权
    测试半导体器件中的保险丝配置

    公开(公告)号:US08063650B2

    公开(公告)日:2011-11-22

    申请号:US12008318

    申请日:2008-01-10

    IPC分类号: G01R31/10 G01R31/26

    摘要: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

    摘要翻译: 用于测试半导体器件的方法,系统和设备。 半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。 半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路,以及包括保险丝的熔丝电路,并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。 熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

    Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells
    5.
    发明授权
    Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells 有权
    由用作DRAM单元和EPROM单元的多个单晶体管单元形成的部分非易失性动态随机存取存储器

    公开(公告)号:US06266272B1

    公开(公告)日:2001-07-24

    申请号:US09364841

    申请日:1999-07-30

    IPC分类号: G11C1450

    CPC分类号: G11C16/02 G11C11/005

    摘要: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.

    摘要翻译: 部分非易失性动态随机存取存储器(PNDRAM)使用由多个单晶体管(1T)单元或两个晶体管(2T)单元形成的DRAM阵列。 电池可电可编程为非易失性存储器。 这导致具有动态随机存取存储器(DRAM)和电可编程只读存储器(EPROM)的单芯片设计。 集成在PNDRAM中的DRAM和EPROM可以随时重新配置,无论是在制造还是在现场。 PNDRAM具有多个应用,例如将主内存与ID,BIOS或操作系统信息组合在一个芯片中。

    Testing fuse configurations in semiconductor devices
    6.
    发明申请
    Testing fuse configurations in semiconductor devices 有权
    测试半导体器件中的保险丝配置

    公开(公告)号:US20080278190A1

    公开(公告)日:2008-11-13

    申请号:US12008318

    申请日:2008-01-10

    IPC分类号: H01L23/62 G01R31/26

    摘要: Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

    摘要翻译: 用于测试半导体器件的方法,系统和设备。 半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。 半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路,以及包括保险丝的熔丝电路,并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。 熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。