公开(公告)号：US06266272B1

公开(公告)日：2001-07-24

申请号：US09364841

申请日：1999-07-30

申请人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

发明人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

IPC分类号： G11C1450

CPC分类号： G11C16/02 ,  G11C11/005

摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.

摘要翻译： 部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。 电池可电可编程为非易失性存储器。 这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。 集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。

公开(公告)号：US20070001708A1

公开(公告)日：2007-01-04

申请号：US11531140

申请日：2006-09-12

申请人： Claude Bertin ,  Wayne Ellis ,  Mark Kellogg ,  William Tonti ,  Jerzy Zalesinski ,  James Leas ,  Wayne Howell

发明人： Claude Bertin ,  Wayne Ellis ,  Mark Kellogg ,  William Tonti ,  Jerzy Zalesinski ,  James Leas ,  Wayne Howell

IPC分类号： G01R31/26

CPC分类号： G01R31/2867 ,  G11C5/04 ,  G11C29/06 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56016 ,  G11C29/785 ,  G11C2029/2602 ,  G11C2029/5602 ,  H01L22/22 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

摘要翻译： 在载体上提供多个半导体器件用于测试或烧录。 然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。 载体用作每个芯片的第一级封装。 因此，载体用于测试和烧录和包装的双重目的。 可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。 切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。 最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。 堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

公开(公告)号：US20050145983A1

公开(公告)日：2005-07-07

申请号：US11055106

申请日：2005-02-11

申请人： Claude Bertin ,  Ramachandra Divakaruni ,  Russell Houghton ,  Jack Mandelman ,  William Tonti

发明人： Claude Bertin ,  Ramachandra Divakaruni ,  Russell Houghton ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

公开(公告)号：US20080050866A1

公开(公告)日：2008-02-28

申请号：US11927780

申请日：2007-10-30

申请人： Roger Booth ,  Jack Mandelman ,  William Tonti

发明人： Roger Booth ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/336

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

公开(公告)号：US20080029843A1

公开(公告)日：2008-02-07

申请号：US11873197

申请日：2007-10-16

申请人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

发明人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L29/41

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

摘要翻译： 一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

公开(公告)号：US20070284669A1

公开(公告)日：2007-12-13

申请号：US11838934

申请日：2007-08-15

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： B07C5/344 ,  G01R31/2831

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20070241768A1

公开(公告)日：2007-10-18

申请号：US11760575

申请日：2007-06-08

申请人： KARL ERICKSON ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

发明人： KARL ERICKSON ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

IPC分类号： G11C8/20

CPC分类号： G06F21/71

摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).

摘要翻译： 提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。 操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。

公开(公告)号：US20070210411A1

公开(公告)日：2007-09-13

申请号：US11372334

申请日：2006-03-09

申请人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。

公开(公告)号：US20070205485A1

公开(公告)日：2007-09-06

申请号：US11366879

申请日：2006-03-02

申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： Programmable anti-fuse structures for semiconductor device constructions, fabrication methods for forming anti-fuse structures during semiconductor device fabrication, and programming methods for anti-fuse structures. The programmable anti-fuse structure comprises first and second terminals and an anti-fuse layer electrically coupled with the first and second terminals. An electrically-conductive diffusion layer is disposed between the first terminal and the anti-fuse layer. The diffusion layer inhibits diffusion of conductive material from the first terminal to the anti-fuse layer when the anti-fuse structure is unprogrammed, but permits diffusion of the conductive material when a programming voltage is applied between the first and second terminals during operation. Advantageously, the first terminal may be composed of metal and the anti-fuse layer may be composed of a semiconductor. The methods of fabricating the anti-fuse structure do not require an additional lithographic mask but instead rely on damascene process steps used to fabricate interconnection structures for neighboring active devices.

摘要翻译： 用于半导体器件结构的可编程抗熔丝结构，在半导体器件制造期间形成抗熔丝结构的制造方法以及用于抗熔丝结构的编程方法。 可编程反熔丝结构包括第一和第二端子以及与第一和第二端子电耦合的抗熔丝层。 导电扩散层设置在第一端子和反熔丝层之间。 当反熔丝结构未编程时，扩散层抑制导电材料从第一端子到抗熔丝层的扩散，但是当在操作期间在第一和第二端子之间施加编程电压时允许导电材料的扩散。 有利地，第一端子可以由金属构成，并且抗熔丝层可以由半导体构成。 制造抗熔丝结构的方法不需要额外的光刻掩模，而是依赖用于制造相邻有源器件的互连结构的镶嵌工艺步骤。

公开(公告)号：US20070190740A1

公开(公告)日：2007-08-16

申请号：US11733249

申请日：2007-04-10

申请人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

发明人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

IPC分类号： H01L21/76

CPC分类号： H01L29/78687 ,  H01L21/26533 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78603

摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.

摘要翻译： 提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。 增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。 在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。