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公开(公告)号:US20050010713A1
公开(公告)日:2005-01-13
申请号:US10716066
申请日:2003-11-18
申请人: Darren Neuman , Sathish Radhakrishnan , Jeffrey Fisher , Joshua Stults , Nitin Borle , Kaushik Bhattacharya
发明人: Darren Neuman , Sathish Radhakrishnan , Jeffrey Fisher , Joshua Stults , Nitin Borle , Kaushik Bhattacharya
CPC分类号: G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C2207/107 , G11C2207/2254
摘要: Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: acquiring a plurality of statistics, the plurality of statistics defining an operating region for the DDR memory controller; and calculating optimal values for the plurality of NCDLs, the optimal values calculated using the plurality of statistics.
摘要翻译: 本文给出了优化DDR存储器控制器中的多个数控延迟线(NCDLS)的方法。 在一个实施例中,方法可以包括例如以下中的一个或多个:获取多个统计,所述多个统计定义了DDR存储器控制器的操作区域; 以及计算所述多个NCDL的最佳值,所述最优值使用所述多个统计量计算。
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公开(公告)号:US07111111B2
公开(公告)日:2006-09-19
申请号:US10716066
申请日:2003-11-18
申请人: Darren Neuman , Sathish Kumar Radhakrishnan , Jeffrey Fisher , Joshua Stults , Nitin Borle , Kaushik Bhattacharya
发明人: Darren Neuman , Sathish Kumar Radhakrishnan , Jeffrey Fisher , Joshua Stults , Nitin Borle , Kaushik Bhattacharya
IPC分类号: G06F12/00
CPC分类号: G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C2207/107 , G11C2207/2254
摘要: Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: acquiring a plurality of statistics, the plurality of statistics defining an operating region for the DDR memory controller; and calculating optimal values for the plurality of NCDLs, the optimal values calculated using the plurality of statistics.
摘要翻译: 本文给出了优化DDR存储器控制器中的多个数控延迟线(NCDLS)的方法。 在一个实施例中,方法可以包括例如以下中的一个或多个:获取多个统计,所述多个统计定义了DDR存储器控制器的操作区域; 以及计算所述多个NCDL的最佳值,所述最优值使用所述多个统计量计算。
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