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    MEMORY POWER MANAGER
    1.
    发明申请
    MEMORY POWER MANAGER 有权
    内存电源管理器

    公开(公告)号：US20110276817A1

    公开(公告)日：2011-11-10

    申请号：US12774479

    申请日：2010-05-05

    Applicant: Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty

    Inventor： Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty

    IPC: G06F1/32 ,  G06F12/00 ,  G06F1/00

    CPC classification number: G06F13/1668 ,  G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

    Abstract translation: 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。 考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。 定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行（同时）在硬件中执行。

    System and method to align clock signals
    2.
    发明授权
    System and method to align clock signals 失效
    系统和方法来对齐时钟信号

    公开(公告)号：US07430680B2

    公开(公告)日：2008-09-30

    申请号：US11169006

    申请日：2005-06-29

    Applicant: Lionel J. D'Luna ,  Thomas A. Hughes ,  Sathish Kumar Radhakrishnan

    Inventor： Lionel J. D'Luna ,  Thomas A. Hughes ,  Sathish Kumar Radhakrishnan

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  G06F1/12

    Abstract: A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal. These subsequent delay device clock signals are transmitted to the aligning device and to the sequencer before each transfer occurs.

    Abstract translation: 在它们之间的数据传输之前，系统和方法使用对准装置对准两个逻辑装置的时钟信号。 在该示例中，对准装置在定序器将数据传送到存储装置之前将定序器的时钟信号与存储装置的时钟信号对准。 对准装置包括相位检测器，其接收用于控制存储装置的第一参考时钟信号和用于控制定序器的延迟信号，并产生比较时钟信号。 在用于控制与第一参考时钟信号相关的第二参考时钟信号的相位之前，对比较时钟信号进行滤波。 相位控制的第二时钟信号是对准时钟信号，其被反馈到延迟器件以产生与存储器件时钟或第一参考时钟信号对准的一个或多个后续延迟器件时钟信号。 在每次传送发生之前，这些后续的延迟装置时钟信号被发送到对准装置和定序器。

    CONFIGURABLE MEMORY CONTROLLER
    4.
    发明申请
    CONFIGURABLE MEMORY CONTROLLER 审中-公开
    可配置内存控制器

    公开(公告)号：US20110276766A1

    公开(公告)日：2011-11-10

    申请号：US12774462

    申请日：2010-05-05

    Applicant: Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty ,  Lance Flake ,  Vinay Bhasin

    Inventor： Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty ,  Lance Flake ,  Vinay Bhasin

    IPC: G06F12/00

    CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F1/3215 ,  G06F13/1626 ,  H04W52/0274 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D70/142 ,  Y02D70/144

    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

    Abstract translation: 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。 考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。 定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行（同时）在硬件中执行。

    Byte slice based DDR timing closure
    6.
    发明授权
    Byte slice based DDR timing closure 有权
    基于字节片的DDR定时关闭

    公开(公告)号：US07246341B2

    公开(公告)日：2007-07-17

    申请号：US10917693

    申请日：2004-08-13

    Applicant: Lionel D'Luna ,  Tom Hughes ,  Sathish Kumar Radhakrishnan

    Inventor： Lionel D'Luna ,  Tom Hughes ,  Sathish Kumar Radhakrishnan

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5068

    Abstract: Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.

    Abstract translation: 这里提出了一种用于基于字节片的DDR定时关闭的系统和方法。 在一个实施例中，提出了一种用于合成/布置双数据速率存储器的方法，所述方法包括合成/布置双数据速率存储器的一部分; 复制该部分; 并将合成/布置的部分和复制部分放置在相应的多个焊盘附近。

    Memory power manager
    7.
    发明授权
    Memory power manager 有权
    内存电源管理器

    公开(公告)号：US08812889B2

    公开(公告)日：2014-08-19

    申请号：US12774479

    申请日：2010-05-05

    Applicant: Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty

    Inventor： Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty

    IPC: G06F1/26 ,  G06F1/32 ,  G06F13/16

    CPC classification number: G06F13/1668 ,  G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

    Abstract translation: 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。 考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。 定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行（同时）在硬件中执行。

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