公开(公告)号：US06940807B1

公开(公告)日：2005-09-06

申请号：US09699193

申请日：2000-10-26

申请人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

发明人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

IPC分类号： H04J11/00

CPC分类号： G06F17/142 ,  H04L27/2628 ,  H04L27/265

摘要： The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

摘要翻译： 本发明提供一种DSP，其容纳多个当前的X-DSL协议，并且可进一步配置以支持未来的协议。 DSP在传输和接收路径上都具有共享和专用硬件组件。 DSP在宽范围的采样大小和X-DSL协议上实现离散傅立叶变换（DFT）和离散傅立叶逆变换（IDFT）部分。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。 DSP提供与转换的硬件实现相关的速度和仅用于软件的实现的灵活性。 使用基于分组的模式在芯片中调整流量流，其中每个分组与上游和下游数据的特定信道相关联。 每个数据包中的报头和控制信息用于控制每个数据包沿着发送路径或接收路径移动时的处理。 本发明的DSP可有利地用于通信以外的领域，例如：医疗和其他成像，地震分析，雷达和其他军事应用，模式识别，信号处理等。本发明提供一种信号处理架构，其支持 CO / DLC / ONU资源的可扩展性，并且允许对演进的X-DSL标准的显着更灵活的硬件响应，而不必超过硬件资源。 随着标准的发展，硬件可能被重新配置以支持新的标准。

公开(公告)号：US07028063B1

公开(公告)日：2006-04-11

申请号：US09698824

申请日：2000-10-26

申请人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

发明人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

IPC分类号： F06F17/14

CPC分类号： G06F17/141 ,  H04L27/2628 ,  H04L27/265

摘要： A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

摘要翻译： 利用离散电路的傅里叶变换处理器，每个离散电路可配置用于处理各种样本大小的范围。 单个流水线支持例如时域和频域之间的复用双向变换。 在本发明的实施例中，傅里叶变换处理器可以被实现为数字信号处理器（DSP）的一部分。 在该实施例中，DSP可以在宽范围的样本大小和X-DSL协议上实现离散傅里叶变换（DFT）和离散傅里叶逆变换（IDFT）两者。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。

公开(公告)号：US06842429B1

公开(公告)日：2005-01-11

申请号：US09776066

申请日：2001-02-02

申请人： Avadhani Shridhar ,  T. R. Ramesh ,  Raminder S. Bajwa ,  Masoud Eskandari ,  Firooz Massoudi ,  Omprakash S. Sarmaru ,  Behrooz Rezvani

发明人： Avadhani Shridhar ,  T. R. Ramesh ,  Raminder S. Bajwa ,  Masoud Eskandari ,  Firooz Massoudi ,  Omprakash S. Sarmaru ,  Behrooz Rezvani

IPC分类号： H04L12/26 ,  H04L12/66

CPC分类号： H04L12/66

摘要： The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.

摘要翻译： 本发明提供了在单个芯片上支持多个X-DSL协议和多个信道的数字信号处理器。 每个信道被分组化，并且每个分组包括用于控制发送和接收路径上的组件/模块的性能的控制信息。 来自在发送路径和接收路径上包含离散和共享模块的架构的进一步的灵活性。 发送路径和接收路径模块由选择的分组中的控制信息共同控制，并以适当的速率对每个信道的分组进行操作，以及针对该信道的协议。 公开了一种包含这些特征的数字信号处理器（DSP）。 DSP具有良好的外形尺寸，对协议和线路代码的灵活性以及支持的通道数量。