公开(公告)号：US06842429B1

公开(公告)日：2005-01-11

申请号：US09776066

申请日：2001-02-02

申请人： Avadhani Shridhar ,  T. R. Ramesh ,  Raminder S. Bajwa ,  Masoud Eskandari ,  Firooz Massoudi ,  Omprakash S. Sarmaru ,  Behrooz Rezvani

发明人： Avadhani Shridhar ,  T. R. Ramesh ,  Raminder S. Bajwa ,  Masoud Eskandari ,  Firooz Massoudi ,  Omprakash S. Sarmaru ,  Behrooz Rezvani

IPC分类号： H04L12/26 ,  H04L12/66

CPC分类号： H04L12/66

摘要： The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.

摘要翻译： 本发明提供了在单个芯片上支持多个X-DSL协议和多个信道的数字信号处理器。 每个信道被分组化，并且每个分组包括用于控制发送和接收路径上的组件/模块的性能的控制信息。 来自在发送路径和接收路径上包含离散和共享模块的架构的进一步的灵活性。 发送路径和接收路径模块由选择的分组中的控制信息共同控制，并以适当的速率对每个信道的分组进行操作，以及针对该信道的协议。 公开了一种包含这些特征的数字信号处理器（DSP）。 DSP具有良好的外形尺寸，对协议和线路代码的灵活性以及支持的通道数量。

公开(公告)号：US06940807B1

公开(公告)日：2005-09-06

申请号：US09699193

申请日：2000-10-26

申请人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

发明人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

IPC分类号： H04J11/00

CPC分类号： G06F17/142 ,  H04L27/2628 ,  H04L27/265

摘要： The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

摘要翻译： 本发明提供一种DSP，其容纳多个当前的X-DSL协议，并且可进一步配置以支持未来的协议。 DSP在传输和接收路径上都具有共享和专用硬件组件。 DSP在宽范围的采样大小和X-DSL协议上实现离散傅立叶变换（DFT）和离散傅立叶逆变换（IDFT）部分。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。 DSP提供与转换的硬件实现相关的速度和仅用于软件的实现的灵活性。 使用基于分组的模式在芯片中调整流量流，其中每个分组与上游和下游数据的特定信道相关联。 每个数据包中的报头和控制信息用于控制每个数据包沿着发送路径或接收路径移动时的处理。 本发明的DSP可有利地用于通信以外的领域，例如：医疗和其他成像，地震分析，雷达和其他军事应用，模式识别，信号处理等。本发明提供一种信号处理架构，其支持 CO / DLC / ONU资源的可扩展性，并且允许对演进的X-DSL标准的显着更灵活的硬件响应，而不必超过硬件资源。 随着标准的发展，硬件可能被重新配置以支持新的标准。

公开(公告)号：US06937616B1

公开(公告)日：2005-08-30

申请号：US09620779

申请日：2000-07-21

申请人： Behrooz Rezvani ,  Sam Heidari ,  Avadhani Shridhar ,  Omprakash S. Samaru ,  Firooz Massoudi

发明人： Behrooz Rezvani ,  Sam Heidari ,  Avadhani Shridhar ,  Omprakash S. Samaru ,  Firooz Massoudi

IPC分类号： H04J3/22 ,  H04L12/28 ,  H04M11/06

CPC分类号： H04L12/2883 ,  H04L12/2856 ,  H04M11/062

摘要： A method and apparatus for digital subscriber line (xDSL) communications between one or more digital signal processors (DSPs) and analog front ends (AFEs) each coupled to corresponding subscriber line(s). The apparatus transports channels of data between subscribers and the DSP(s). The apparatus includes a bus for the transport of digital data, a DSP AFE interfaces. The DSP interfaces couples the DSP to the bus. The DSP interface accepts downstream channels of digital data from the DSP and transmits packets each associated with a corresponding one of the downstream channels to the bus. Each of the packets identifies a targeted AFEs coupled to a selected one of the subscriber lines. The AFE interfaces each couple an associated one of the AFEs to the bus. Each of the AFE interfaces transmits selected packets to a selected one of the subscriber lines for the transport to the subscriber.

摘要翻译： 一种用于一个或多个数字信号处理器（DSP）和模拟前端（AFE）之间的数字用户线（xDSL）通信的方法和装置，每个耦合到对应的用户线路。 该设备在订户和DSP之间传输数据信道。 该装置包括用于传输数字数据的总线，DSP AFE接口。 DSP接口将DSP耦合到总线。 DSP接口接收来自DSP的数字数据的下行信道，并且将与相应的一个下行信道相关联的分组发送到总线。 每个分组识别耦合到所选择的一个用户线路的目标AFE。 AFE接口将每个AFE接口中的一个耦合到总线。 每个AFE接口将所选择的分组传送到所选择的一个用户线，以便传输给用户。

公开(公告)号：US06708307B1

公开(公告)日：2004-03-16

申请号：US09709689

申请日：2000-11-10

申请人： Firooz Massoudi

发明人： Firooz Massoudi

IPC分类号： H03M1300

CPC分类号： G11B20/16 ,  G11B20/18 ,  H03M13/00

摘要： Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

摘要翻译： 公开了一种用于可靠地检测CD-ROM介质中的同步模式的外围设备。 外围设备具有用于控制和处理从外围设备的介质读取的数据的内部电路。 外围设备包括数字信号处理器，解码器电路和状态机。 数字信号处理器被配置为从外围设备的介质接收正在读取的数据。 解码器电路耦合到数字信号处理器并形成内部电路的一部分。 此外，解码器电路包括内部RAM，其被配置为存储包括当前同步模式和下一个同步模式的数据的扇区。 状态机驻留在解码器中，用于分析数据的扇区的当前同步模式和下一个同步模式。 在分析模式中，状态码被配置为确定数据中是否存在致命错误。

公开(公告)号：US06173430B2

公开(公告)日：2001-01-09

申请号：US09023169

申请日：1998-02-13

申请人： Firooz Massoudi

发明人： Firooz Massoudi

IPC分类号： H03M1300

CPC分类号： G11B20/16 ,  G11B20/18 ,  H03M13/00

摘要： Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

摘要翻译： 公开了一种用于可靠地检测CD-ROM介质中的同步模式的外围设备。 外围设备具有用于控制和处理从外围设备的介质读取的数据的内部电路。 外围设备包括数字信号处理器，解码器电路和状态机。 数字信号处理器被配置为从外围设备的介质接收正在读取的数据。 解码器电路耦合到数字信号处理器并形成内部电路的一部分。 此外，解码器电路包括内部RAM，其被配置为存储包括当前同步模式和下一个同步模式的数据的扇区。 状态机驻留在解码器中，用于分析数据的扇区的当前同步模式和下一个同步模式。 在分析模式中，状态码被配置为确定数据中是否存在致命错误。

公开(公告)号：US06260169B1

公开(公告)日：2001-07-10

申请号：US09052917

申请日：1998-03-31

申请人： Firooz Massoudi

发明人： Firooz Massoudi

IPC分类号： G11C2900

CPC分类号： H03M13/2927 ,  G11B20/10 ,  H03M13/2906

摘要： Disclosed is a device for performing a header and row correction on rows of sector data that are read sequentially from a DVD medium. The device includes a pair of row buffers, a syndrome generator, and an error correction circuitry. The pair of row buffers sequentially receives and stores a current row of the sector data. When one buffer is receiving a next row of the sector data and is functioning as a receive buffer, the other buffer stores the current row of the sector data and functions as a correction buffer to be used in error correction. The syndrome generator receives the current row of the sector data and is configured to sequentially generate a row syndrome for the current row. The row syndrome is configured to indicates whether an error is present in the current row that is stored in the correction buffer. The error correction circuitry is coupled to the syndrome generator and is configured to receive the row syndrome associated with the current row that is stored in the correction buffer. The error correction circuitry is configured to correct the error that is present in the current row that is contained in the correction buffer.

摘要翻译： 公开了一种用于对从DVD介质顺序读取的扇区数据行执行报头和行校正的装置。 该装置包括一对行缓冲器，校正子发生器和纠错电路。 一对行缓冲器顺序地接收并存储扇区数据的当前行。 当一个缓冲器正在接收扇区数据的下一行并且用作接收缓冲器时，另一个缓冲器存储扇区数据的当前行并且用作纠正用于纠错的校正缓冲器。 校正子发生器接收扇区数据的当前行并被配置为顺序地生成用于当前行的行综合征。 行校验子被配置为指示存储在校正缓冲器中的当前行中是否存在错误。 误差校正电路被耦合到校正子发生器，并被配置为接收与存储在校正缓冲器中的当前行相关联的行校正。 错误校正电路被配置为校正在校正缓冲器中包含的当前行中存在的错误。

公开(公告)号：US07191387B1

公开(公告)日：2007-03-13

申请号：US10392674

申请日：2003-03-18

申请人： Firooz Massoudi

发明人： Firooz Massoudi

IPC分类号： H03M13/03

CPC分类号： H03M13/4169 ,  H03M13/4107 ,  H03M13/6561

摘要： A convolutional decoder for a wired or wireless receiver receiving an encoded datastream. The branch and path metric components compute branch and path metrics for the encoded datastream stream. The traceback unit couples to the path metric component to trace in each traceback interval a single path through the path metrics to determine correction factors for decoding at least two corresponding successive sub-symbols/symbols from the encoded datastream in each traceback interval.

摘要翻译： 用于有线或无线接收器的卷积解码器接收编码数据流。 分支和路径度量组件计算编码数据流流的分支和路径度量。 回溯单元耦合到路径度量组件，以在每个回溯间隔中跟踪通过路径度量的单个路径，以确定用于在每个回溯间隔中从编码数据流解码至少两个对应的连续子符号/符号的校正因子。

公开(公告)号：US06363511B1

公开(公告)日：2002-03-26

申请号：US09052912

申请日：1998-03-31

申请人： Firooz Massoudi

发明人： Firooz Massoudi

IPC分类号： H03M1329

CPC分类号： H03M13/1515 ,  G11B20/1833 ,  H03M13/29 ,  H03M13/2909 ,  H03M13/293

摘要： A device for detecting and correcting errors in error correction coded (ECC) data blocks that are read sequentially from a DVD medium is disclosed. Each ECC data block is defined as a two dimensional block of a plurality of columns and rows. Each of the ECC data blocks is read from the DVD medium sequentially in rows. The device includes row correction circuitry, a buffer, column correction circuitry, and repeat correction circuitry. The row correction circuitry is configured to sequentially receive the rows of an ECC data block for detecting and correcting up to a first predetermined number of errors in each of the received rows. The buffer is coupled to the row correction circuitry for receiving the error corrected rows of the ECC data block as a receiving buffer. The buffer also stores the ECC data block as a correction buffer when all the rows of the ECC data block have received. The column correction circuitry is coupled to the row correction circuitry and the buffer to sequentially receive the row error corrected rows of the ECC data block for detecting the uncorrected errors. The column correction circuitry is also configured to correct the uncorrected errors in the columns of the ECC data block that is stored in the correction buffer. The repeat correction circuitry is coupled to the buffer for detecting and correcting the remaining uncorrected errors in the correction buffer.

摘要翻译： 公开了一种用于检测和校正从DVD介质顺序读取的纠错编码（ECC）数据块中的错误的装置。 每个ECC数据块被定义为多个列和行的二维块。 ECC数据块中的每一个依次从DVD介质中读取。 该装置包括行校正电路，缓冲器，列校正电路和重复校正电路。 行校正电路被配置为顺序地接收ECC数据块的行，用于在每个接收的行中检测和校正高达第一预定数量的错误。 缓冲器耦合到行校正电路，用于接收作为接收缓冲器的ECC数据块的纠错行。 当ECC数据块的所有行已经接收到时，缓冲器还将ECC数据块存储为校正缓冲器。 列校正电路耦合到行校正电路和缓冲器以顺序地接收ECC数据块的行纠错行，以检测未校正的错误。 列校正电路还被配置为校正存储在校正缓冲器中的ECC数据块的列中的未校正错误。 重复校正电路耦合到缓冲器，用于检测和校正校正缓冲器中剩余的未校正误差。

公开(公告)号：US4984287A

公开(公告)日：1991-01-08

申请号：US271452

申请日：1988-11-15

申请人： Firooz Massoudi

发明人： Firooz Massoudi

IPC分类号： G06F3/03 ,  G06F3/033 ,  G06F3/039 ,  G06T1/00 ,  H04N1/047 ,  H04N1/107

CPC分类号： G06F3/0317 ,  G06F3/03544 ,  H04N1/047 ,  H04N1/107 ,  H04N2201/0422 ,  H04N2201/04729 ,  H04N2201/04789

摘要： A method for orienting a dual mouse optical scanner on an orthogonal grid pattern comprising the steps of (a) placing a dual mouse scanner on a grid pattern at a small angle to the vertical lines of the grid pattern and commencing motion detection with the two mice, (b) setting the coordinate position of each mouse at (0,0), (c) rotating the scanner in a predetermined manner while measuring the vertical distance on the grid pattern between the two mice for each new position of the scanner, (d) determining an average scanner position amongst all scanner positions having the same maximum vertical grid distance between the mice, and (e) establishing the coordinate position of one mouse at the average scanner position as the origin of a coordinate system in the memory of a computer in communication with the scanner and the vertical line closest to the origin and the coordinate position of the other mouse as the vertical axis of the coordinate system.

摘要翻译： 一种用于在正交网格图案上定向双鼠标光学扫描仪的方法，包括以下步骤：（a）将双鼠标扫描仪放置在与网格图案的垂直线成小角度的网格图案上，并且与两只小鼠开始运动检测 ，（b）将每个鼠标的坐标位置设置为（0,0），（c）以预定的方式旋转扫描仪，同时测量扫描仪的每个新位置的两只小鼠之间的网格图案上的垂直距离（ d）确定在具有相同的鼠标之间的最大垂直网格距离的所有扫描器位置之间的平均扫描器位置，以及（e）在平均扫描器位置处建立一个鼠标在坐标系的原点的坐标位置 计算机与扫描仪通信，最靠近原点的垂直线和另一鼠标的坐标位置作为坐标系的垂直轴。