METHOD AND APPARATUS FOR SOLVING SYSTEM OF NONLINEAR EQUATIONS BASED ON QUANTUM CIRCUIT, AND STORAGE MEDIUM

    公开(公告)号:US20240354360A1

    公开(公告)日:2024-10-24

    申请号:US18294765

    申请日:2022-11-25

    CPC classification number: G06F17/11 G06F17/16 G06N10/20

    Abstract: A method for solving a system of nonlinear equations on the basis of a quantum circuit includes acquiring a target system of nonlinear equations to be solved, converting the target system to obtain a target system of linear equations, constructing a quantum circuit corresponding to a quantum linear solver used for solving the target system, performing, based on the quantum circuit corresponding to the quantum linear solver, quantum state evolution and measurement on the target system, to solve the target system, and determining, based on an obtained solution of the target system, a solution of the target system to be solved. With the method, the complexity and difficulty in solving a system of nonlinear equations may be reduced, thereby filling in related technical gaps in the field of quantum computation.

    Method and device for quantum division operation with precision

    公开(公告)号:US12086569B2

    公开(公告)日:2024-09-10

    申请号:US18029558

    申请日:2021-09-17

    Inventor: Ye Li Menghan Dou

    CPC classification number: G06F7/575 G06F7/4824 G06N10/20

    Abstract: A method and device for quantum division operation with precision. The method includes: obtaining dividend data and divisor data to be operated, transforming the dividend data into a first target quantum state, and transforming the divisor data into a second target quantum state; for the first target quantum state and the second target quantum state, iteratively executing quantum state evolution corresponding to a subtraction operation, counting the number of executions of the subtraction operation until the dividend data is reduced to a negative number, and outputting a finally obtained counting result as integer part of a quotient of dividing the dividend data by the divisor data; for a current first target quantum state and a current second target quantum state, iteratively executing quantum state evolution corresponding to fractional part operation of the quotient; and outputting a finally obtained quantum state on a qubit with preset precision bits.

    Quantum convolution operator
    4.
    发明授权

    公开(公告)号:US12079691B2

    公开(公告)日:2024-09-03

    申请号:US18278723

    申请日:2022-02-23

    CPC classification number: G06N10/20

    Abstract: The present disclosure provides a quantum convolution operator, comprising: a quantum state encoding module, a quantum entanglement module, a quantum convolution kernel module, a measuring module, and a computing module; the quantum state encoding module is configured to encode a current group of input data onto qubits; the quantum entanglement module is configured to associate quantum state information of different qubits; the quantum convolution kernel module is configured to extract feature information corresponding to the quantum state information; the measuring module is configured to measure a quantum state of a preset qubit and obtain a corresponding amplitude; the computing module is configured to compute a convolution result corresponding to the current group of input data according to the measured quantum state and its amplitude.

    Method and apparatus for amplitude estimation of quantum circuit, storage medium, and electronic apparatus

    公开(公告)号:US11900220B2

    公开(公告)日:2024-02-13

    申请号:US18310405

    申请日:2023-05-01

    CPC classification number: G06N10/20 G06N10/60

    Abstract: Disclosed are a method and an apparatus for amplitude estimation of a quantum circuit. The method includes: calculating a first difference value between a current angle upper limit value and a current angle lower limit value corresponding to a to-be-estimated amplitude of a target quantum state, and determining the first difference value as a target difference; determining, a next angle amplification factor and a next flag parameter corresponding to a next iteration step; amplifying the target quantum circuit by the next angle amplification factor; calculating a second difference value between a next angle upper limit value and a next angle lower limit value of the to-be-estimated amplitude, and determining the second difference value as a target difference; and determining, based on an angle upper limit value and an angle lower limit value that reach the precision threshold, a probability estimated value corresponding to a to-be-estimated quantum bit.

    Quantum parameter amplifier
    6.
    发明授权

    公开(公告)号:US11894818B2

    公开(公告)日:2024-02-06

    申请号:US17057286

    申请日:2020-03-20

    Inventor: Weicheng Kong

    CPC classification number: H03F7/02 G06N10/00 H01P7/06 H03F19/00 H10N60/805

    Abstract: A quantum parameter amplifier; the quantum parameter amplifier includes a capacitor module, a first microwave resonant cavity, and an inductance-adjustable superconducting quantum interference apparatus that are connected in sequence to constitute an oscillation amplifier circuit, wherein, the superconducting quantum interference apparatus is grounded; the quantum parameter amplifier further includes a voltage modulating circuit and/or a second microwave resonant cavity; one end of the voltage modulating circuit is connected with an end of the superconducting quantum interference apparatus that is close to the first microwave resonant cavity; and one end of the second microwave resonant cavity is connected with the end of the superconducting quantum interference apparatus that is close to the first microwave resonant cavity. A frequency of a pump signal that makes the quantum parameter amplifier according to the present disclosure in an optimal operation mode does not need to be selected as a multiple of a frequency of the signal to be amplified.

    SYNCHRONOUS TRIGGERING SYSTEM, QUANTUM CONTROL SYSTEM AND QUANTUM COMPUTER

    公开(公告)号:US20250047281A1

    公开(公告)日:2025-02-06

    申请号:US18718668

    申请日:2022-10-27

    Abstract: Disclosed are a synchronous triggering system, a quantum control system and a quantum computer. The synchronous triggering system comprises a central control device, several routing boards and several functional boards. It guarantees the synchronous triggering of the triggering signals by means of a three-stage triggering synchronization system. In the first stage, the central control device provides several sets of triggering signals to corresponding routing boards, and adjusts an initial time point for each set of triggering signals to output so that each chassis receives the triggering signals concurrently. In the second stage, communication lines from each routing board to the several functional boards are of equal length. In the third stage, the triggering signals arrive at several data-processing devices simultaneously after being processed under the AND-operation of an AND-gate chip.

    Fabrication method for superconducting circuit and superconducting quantum chip

    公开(公告)号:US12207568B2

    公开(公告)日:2025-01-21

    申请号:US18315401

    申请日:2023-05-10

    Abstract: Disclosed are a fabrication method for a superconducting circuit and a superconducting quantum chip. The fabrication method includes: determining, on a substrate, a first junction region located between a first electrical element and a second electrical element, and a second junction region located between a first conductive plate and a second conductive plate that are formed in advance; forming a Josephson junction in the second junction region; detect an electrical parameter of the Josephson junction, and determining whether the electrical parameter is within a target parameter range; if yes, separating the Josephson junction through cutting, and moving the Josephson junction to the first junction region; and forming a first connection structure connecting the first superconducting layer to the first electrical element and a second connection structure connecting the second superconducting layer to the second electrical element.

    METHOD, APPARATUS, TERMINAL AND STORAGE MEDIUM FOR QUANTUM TOPOLOGY GRAPH OPTIMIZATION

    公开(公告)号:US20240289663A1

    公开(公告)日:2024-08-29

    申请号:US18434090

    申请日:2024-02-06

    Inventor: Weicheng KONG

    CPC classification number: G06N10/20 G06F30/398

    Abstract: Disclosed are a quantum topology graph optimization method, apparatus, terminal and storage medium, comprising: obtaining a first quantum topology graph of a target quantum algorithm, determining an intermediate node in the first quantum topology graph, and removing connecting lines between other graph nodes other than the intermediate node so as to obtain a second quantum topology graph without the crossed connecting lines; if not, updating the first quantum topology graph to a third quantum topology graph; determining an optimized sub-graph corresponding to one node to be optimized and composed of N child nodes connected by connecting lines according to a preset way, assigning connecting lines between non-optimized nodes and each child node so as to obtain a fourth quantum topology graph; restoring connecting lines between non-optimized nodes in the fourth quantum topology graph so as to obtain an optimized quantum topology graph.

    QUANTUM COMPUTER OPERATING SYSTEM AND QUANTUM COMPUTER

    公开(公告)号:US20240231947A9

    公开(公告)日:2024-07-11

    申请号:US18400209

    申请日:2023-12-29

    CPC classification number: G06F9/5066 G06N10/60

    Abstract: Disclosed are a quantum computer operating system and a quantum computer. In the operating system, if the quantity of the free qubits on a certain chip in the quantum chip cluster is not less than the quantity required by the quantum computing task, selecting a first quantum bit whose reading fidelity is within a preset range from the free qubits and obtaining a nearby pair of quantum bits based on the community detection algorithm and the greedy algorithm, and combining them to form a qubit topological structure until the number of quantum bits is equal to the number required by the quantum computing task. Finally, mapping the quantum computing task to be processed with the qubit topological structure to execute the quantum computing task to be processed.

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