公开(公告)号：US06509759B1

公开(公告)日：2003-01-21

申请号：US10073541

申请日：2002-02-11

申请人： Owen J. Hynes

发明人： Owen J. Hynes

IPC分类号： H03K190185

CPC分类号： H03K17/102 ,  H03K17/08122 ,  H03K19/00315

摘要： A circuit is protected from the application voltage from a high and a low voltage source that may power up at different times by supplying a circuit the applies an intermediate voltage whenever the high voltage has powered up when the low voltage has not until such time as the low voltage has powered up.

摘要翻译： 保护电路免受来自高电压源和低电压源的施加电压的影响，该高电压源和低电压源可以在不同时间通过供电电路加电，每当高电压直到下一次 低电压上电。

公开(公告)号：US07426133B2

公开(公告)日：2008-09-16

申请号：US11257327

申请日：2005-10-24

申请人： Owen J. Hynes ,  Roy R. Wang ,  Romney R. Katti ,  Daniel S. Reed

发明人： Owen J. Hynes ,  Roy R. Wang ,  Romney R. Katti ,  Daniel S. Reed

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： A magneto-resistive memory system is presented that includes a radiation-hardened and low power memory cell. The magneto-resistive memory cell includes a word line select transistor in the cell to help eliminate unselected cell disturbances. Furthermore, the magneto-resistive memory cell includes a full-turn write word line that writes true and complimentary bit values using less current than previous cell architectures. The improved memory cell may be used in a memory system with precision current drivers and auto-zero sense amplifiers in order to further lower power and improve overall system reliability.

摘要翻译： 提出了一种包含辐射硬化和低功率存储单元的磁阻存储器系统。 磁阻存储单元包括单元中的字线选择晶体管，以帮助消除未选择的单元干扰。 此外，磁阻存储器单元包括使用比以前的单元架构更少的电流写入真实和互补位值的全匝写入字线。 改进的存储单元可以用于具有精密电流驱动器和自动零感测放大器的存储器系统中，以便进一步降低功率并提高整体系统的可靠性。

公开(公告)号：US06518818B1

公开(公告)日：2003-02-11

申请号：US09954251

申请日：2001-09-17

申请人： Owen J. Hynes

发明人： Owen J. Hynes

IPC分类号： H03L500

CPC分类号： H03K19/00315

摘要： A high-voltage output buffer is implemented in a low-voltage semiconductor process. The buffer comprises a level translator circuit, the level translator operable to receive a signal varying between ground and a low voltage level, and to output a corresponding signal varying between a reference voltage level and a high voltage level. The reference voltage level is an intermediate voltage level between half of the low voltage level and the high voltage level. The buffer further comprises an output circuit operable to receive via an input the output of the level translator circuit, and to output a high voltage level when the input is a high voltage level or a zero voltage level when the input is at the reference voltage level.

摘要翻译： 在低电压半导体工艺中实现高压输出缓冲器。 缓冲器包括电平转换器电路，电平转换器可操作以接收在接地和低电压电平之间变化的信号，并输出在参考电压电平和高电压电平之间变化的相应信号。 参考电压电平是低电平电平的一半和高电压电平之间的中间电压电平。 该缓冲器还包括输出电路，其可操作以经由输入端接收电平转换器电路的输出，并且当输入为基准电压电平时输入为高电压电平或零电压电平时输出高电压电平 。

公开(公告)号：US07466181B2

公开(公告)日：2008-12-16

申请号：US11185262

申请日：2005-07-20

申请人： Owen J. Hynes

发明人： Owen J. Hynes

IPC分类号： H03K3/00 ,  H03L5/00

CPC分类号： H01L27/0285

摘要： A novel system for protecting one or more circuits during a dose rate event is presented. A clamping circuit is utilized that outputs a voltage signal that may be used to control prevent circuits from receiving input signals during a dose rate event. The clamping circuit comprises a photocurrent generating device that creates a current as a function of dose rate event strength. This current is used to control a grounding switch, which pulls the clamping circuit output to ground when a substantial current is created by the photocurrent generating device. The clamping circuit output may control a coupling switch that permits external input signal current flow when the clamping circuit output is above a threshold voltage level, and may prevent current flow when the output is grounded. The photocurrent generating device may be a PMOS device, while the coupling switch and clamping switch may be realized by NMOS devices.

摘要翻译： 提出了一种用于在剂量率事件期间保护一个或多个电路的新型系统。 使用钳位电路，其输出可用于控制阻止电路在剂量率事件期间接收输入信号的电压信号。 钳位电路包括光电流产生装置，其产生作为剂量率事件强度的函数的电流。 该电流用于控制接地开关，当由光电流产生装置产生大量电流时，该接地开关将钳位电路输出接地。 当钳位电路输出高于阈值电压电平时，钳位电路输出可以控制允许外部输入信号电流流动的耦合开关，并且可以在输出接地时防止电流流动。 光电流产生装置可以是PMOS器件，而耦合开关和钳位开关可以由NMOS器件实现。

公开(公告)号：US07248496B2

公开(公告)日：2007-07-24

申请号：US11273214

申请日：2005-11-14

申请人： Romney R. Katti ,  Owen J. Hynes ,  Daniel S. Reed ,  Hassan Kaakani

发明人： Romney R. Katti ,  Owen J. Hynes ,  Daniel S. Reed ,  Hassan Kaakani

IPC分类号： G11C7/00

CPC分类号： G11C11/16

摘要： A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer. For instance, if the canted resistivity is greater than the uncanted resistivity then the magnetization directions of the pinned and storage layer are parallel, and if the canted resistivity is less than the uncanted resistivity then the magnetization directions of the pinned and storage layer are opposite.

公开(公告)号：US07447061B1

公开(公告)日：2008-11-04

申请号：US11714300

申请日：2007-03-02

申请人： Owen J. Hynes

发明人： Owen J. Hynes

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： An MOS write transistor is connected to write coils of a magnetoresistive memory cell. The MOS write transistor controls passage of a write current into the write coils of the magnetoresistive memory cell. An array of MOS write transistors and an associated array of magnetoresistive memory cells are within a magnetoresistive memory array circuit.

摘要翻译： MOS写入晶体管连接到磁阻存储单元的写入线圈。 MOS写入晶体管控制写入电流流入磁阻存储单元的写入线圈。 MOS写入晶体管阵列和磁阻存储器单元的关联阵列位于磁阻存储器阵列电路内。

公开(公告)号：US07286393B2

公开(公告)日：2007-10-23

申请号：US11096179

申请日：2005-03-31

申请人： Owen J. Hynes ,  Romney Katti ,  Harry H. L. Liu ,  Michael S. Liu

发明人： Owen J. Hynes ,  Romney Katti ,  Harry H. L. Liu ,  Michael S. Liu

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include at least one transistor and/or at least one diode. One device may be used to protect an entire row and/or column of MRAM bits. As a result, the MRAM bits are protected during a dose rate event.

摘要翻译： 器件与MRAM位的MTJ结构并联连接，以在剂量率事件期间跨越MTJ结构分流光电流和/或限制跨越MTJ结构的电压。 该器件可以包括至少一个晶体管和/或至少一个二极管。 一个设备可用于保护MRAM位的整个行和/或列。 结果，在剂量率事件期间MRAM位被保护。

公开(公告)号：US5874845A

公开(公告)日：1999-02-23

申请号：US897860

申请日：1997-07-21

申请人： Owen J. Hynes

发明人： Owen J. Hynes

IPC分类号： H03K5/151 ,  H03H11/22

CPC分类号： H03K5/1515

摘要： A circuit for splitting a clock signal to produce two clock signals of differing phases that do not overlap one another. The circuit includes a NFET, a first PFET, a second NFET and a second PFET. The drain terminals of the first NFET and first PFET are coupled to one another and provide a clock signal FCLKN. The source terminal of the first NFET is coupled to ground, and the source terminal of the first PFET is coupled to the power supply voltage VDD. Similarly, the drain terminals of the second NFET and second PFET are coupled to one another and provide a clock signal FCLK. The source terminal of the second NFET is coupled to ground, and the source terminal of the second PFET is coupled to VDD. The gate terminal of either the first NFET or the first PFET is coupled to a master clock signal. The gate terminal of the other is coupled to the drains of the second NFET and second PFET. Similarly, the gate terminal of the corresponding second NFET or PFET is coupled to the complement of the master clock signal. The gate terminal of the other is coupled to the drains of the first NFET and first PFET. FCLK does not overlap FCLKN because FCLKN cannot change state until FCLK has changed state, and vice versa.

摘要翻译： 用于分离时钟信号以产生不彼此重叠的不同相位的两个时钟信号的电路。 该电路包括NFET，第一PFET，第二NFET和第二PFET。 第一NFET和第一PFET的漏极端子彼此耦合并提供时钟信号FCLKN。 第一NFET的源极端子耦合到地，并且第一PFET的源极端子耦合到电源电压VDD。 类似地，第二NFET和第二PFET的漏极端子彼此耦合并提供时钟信号FCLK。 第二NFET的源极端子耦合到地，并且第二PFET的源极端子耦合到VDD。 第一NFET或第一PFET的栅极端子耦合到主时钟信号。 另一个的栅极端子耦合到第二NFET和第二PFET的漏极。 类似地，相应的第二NFET或PFET的栅极端子耦合到主时钟信号的补码。 另一个的栅极端子耦合到第一NFET和第一PFET的漏极。 FCLK不重叠FCLKN，因为FCLKN在FCLK已经改变状态之前不能改变状态，反之亦然。