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89 条记录 (耗时 0.03 秒)

    MRAM read sequence using canted bit magnetization
    1.
    发明授权
    MRAM read sequence using canted bit magnetization 有权

    公开(公告)号：US07248496B2

    公开(公告)日：2007-07-24

    申请号：US11273214

    申请日：2005-11-14

    申请人： Romney R. Katti ,  Owen J. Hynes ,  Daniel S. Reed ,  Hassan Kaakani

    发明人： Romney R. Katti ,  Owen J. Hynes ,  Daniel S. Reed ,  Hassan Kaakani

    IPC分类号： G11C7/00

    CPC分类号： G11C11/16

    摘要： A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer. For instance, if the canted resistivity is greater than the uncanted resistivity then the magnetization directions of the pinned and storage layer are parallel, and if the canted resistivity is less than the uncanted resistivity then the magnetization directions of the pinned and storage layer are opposite.

    Complementary giant magneto-resistive memory with full-turn word line
    2.
    发明授权
    Complementary giant magneto-resistive memory with full-turn word line 失效
    具有全转字线的互补巨磁阻存储器

    公开(公告)号：US07426133B2

    公开(公告)日：2008-09-16

    申请号：US11257327

    申请日：2005-10-24

    申请人： Owen J. Hynes ,  Roy R. Wang ,  Romney R. Katti ,  Daniel S. Reed

    发明人： Owen J. Hynes ,  Roy R. Wang ,  Romney R. Katti ,  Daniel S. Reed

    IPC分类号： G11C11/00

    CPC分类号： G11C11/15

    摘要： A magneto-resistive memory system is presented that includes a radiation-hardened and low power memory cell. The magneto-resistive memory cell includes a word line select transistor in the cell to help eliminate unselected cell disturbances. Furthermore, the magneto-resistive memory cell includes a full-turn write word line that writes true and complimentary bit values using less current than previous cell architectures. The improved memory cell may be used in a memory system with precision current drivers and auto-zero sense amplifiers in order to further lower power and improve overall system reliability.

    摘要翻译： 提出了一种包含辐射硬化和低功率存储单元的磁阻存储器系统。 磁阻存储单元包括单元中的字线选择晶体管，以帮助消除未选择的单元干扰。 此外，磁阻存储器单元包括使用比以前的单元架构更少的电流写入真实和互补位值的全匝写入字线。 改进的存储单元可以用于具有精密电流驱动器和自动零感测放大器的存储器系统中，以便进一步降低功率并提高整体系统的可靠性。

    Bit end design for pseudo spin valve (PSV) devices
    3.
    发明授权
    Bit end design for pseudo spin valve (PSV) devices 失效
    伪自旋阀（PSV）器件的位端设计

    公开(公告)号：US07183042B2

    公开(公告)日：2007-02-27

    申请号：US10706067

    申请日：2003-11-12

    申请人： Romney R. Katti ,  Paul S. Fechner ,  Gordon A. Shaw ,  Daniel S. Reed ,  David W. Zou

    发明人： Romney R. Katti ,  Paul S. Fechner ,  Gordon A. Shaw ,  Daniel S. Reed ,  David W. Zou

    IPC分类号： G03F7/20

    CPC分类号： G11C11/16

    摘要： In a process of making a magnetoresistive memory device, a mask layout is produced by use of any suitable design tool. The mask layout is laid out in grids having a central grid forming a central section and grids forming bit end sections, and the grids of the bit end sections are rectangles. A mask is made by use of the mask layout, and the mask has stepped bit ends. The mask is used to make a magnetic storage layer having tapered bit ends, to make a magnetic sense layer having tapered bit ends, and to make a non-magnetic layer having tapered bit ends. The non-magnetic layer is between the magnetic sense layer and the magnetic storage layer.

    摘要翻译： 在制造磁阻存储器件的过程中，通过使用任何合适的设计工具来生产掩模布局。 掩模布局布置在具有形成中心部分的中心格栅和形成钻头末端部分的格栅的格栅中，钻头端部的格栅为矩形。 使用掩模布局制作掩模，并且掩模具有阶梯位。 该掩模用于制造具有锥形位端的磁存储层，以形成具有锥形位端的磁感应层，并制成具有锥形位端的非磁性层。 非磁性层位于磁感应层和磁性存储层之间。

    Methods for fabricating giant magnetoresistive (GMR) devices
    4.
    发明授权
    Methods for fabricating giant magnetoresistive (GMR) devices 失效
    制造巨磁阻（GMR）器件的方法

    公开(公告)号：US07383626B2

    公开(公告)日：2008-06-10

    申请号：US11508671

    申请日：2006-08-22

    申请人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

    发明人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

    IPC分类号： G11B5/127 ,  H04R31/00

    CPC分类号： G11C11/16 ,  G11B5/39 ,  H01L43/12 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49155

    摘要： In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

    摘要翻译： 在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。 在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。 图案化磁阻器件层以限定具有侧壁的多个磁性位。 将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。 磁头的侧壁被光致抗蚀剂层覆盖。 使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。 在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。

    Method for fabricating giant magnetoresistive (GMR) devices
    5.
    发明授权
    Method for fabricating giant magnetoresistive (GMR) devices 失效
    制造巨磁阻（GMR）器件的方法

    公开(公告)号：US07114240B2

    公开(公告)日：2006-10-03

    申请号：US10706531

    申请日：2003-11-12

    申请人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

    发明人： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

    IPC分类号： G11B5/127 ,  H04R31/00

    CPC分类号： G11C11/16 ,  G11B5/39 ,  H01L43/12 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49155

    摘要： In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

    摘要翻译： 在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。 在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。 图案化磁阻器件层以限定具有侧壁的多个磁性位。 将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。 磁头的侧壁被光致抗蚀剂层覆盖。 使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。 在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。

    MAGNETIC FIELD SENSING USING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELLS
    6.
    发明申请
    MAGNETIC FIELD SENSING USING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELLS 有权
    使用磁阻随机存取存储器（MRAM）电池进行磁场感测

    公开(公告)号：US20140029334A1

    公开(公告)日：2014-01-30

    申请号：US13561478

    申请日：2012-07-30

    申请人： Romney R. Katti ,  Michael A. Smith

    发明人： Romney R. Katti ,  Michael A. Smith

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C29/04

    摘要： A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source, or another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell.

    摘要翻译： 磁场感测系统包括一个或多个磁阻随机存取存储器（MRAM）单元，并且可以被配置为确定入射到MRAM单元上的外部磁场的存在，大小和极性中的一个或多个。 在一些示例中，系统的控制模块控制写入电流源或另一个器件，以通过与MRAM单元相关联的写入线提供写入电流，以引导靠近MRAM单元的磁场。 磁场可能小于MRAM单元的磁切换阈值。 在开始通过写入线提供写入电流之后，控制模块可以确定MRAM单元的磁状态，并且至少部分地基于MRAM单元的磁状态来确定入射到MRAM单元上的外部磁场的存在 MRAM单元。

    Configurable reference circuit for logic gates
    8.
    发明授权
    Configurable reference circuit for logic gates 有权
    用于逻辑门的可配置参考电路

    公开(公告)号：US08427197B2

    公开(公告)日：2013-04-23

    申请号：US13161070

    申请日：2011-06-15

    申请人： Romney R. Katti

    发明人： Romney R. Katti

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/16

    摘要： This disclosure is directed to techniques for generating a reference current based on a combinational logic function that is to be performed by a magnetic logic device. A comparator circuit may compare an amplitude of a read current that flows through the magnetic logic device and the reference current to generate a logic output value that corresponds to the logic output value when combinational logic function is applied to the input values. By selecting appropriate amplitudes for the reference current the magnetic logic device may be caused to implement different combinational logic functions.

    摘要翻译： 本公开涉及用于基于将由磁逻辑器件执行的组合逻辑功能来产生参考电流的技术。 比较器电路可以比较流过磁逻辑器件的读取电流的幅度和参考电流，以便当将组合逻辑功能应用于输入值时产生对应于逻辑输出值的逻辑输出值。 通过为参考电流选择适当的幅度，可以使磁逻辑器件实现不同的组合逻辑功能。

    Magnetic logic gate
    9.
    发明授权
    Magnetic logic gate 有权
    磁逻辑门

    公开(公告)号：US08358149B2

    公开(公告)日：2013-01-22

    申请号：US12916119

    申请日：2010-10-29

    申请人： Romney R. Katti

    发明人： Romney R. Katti

    IPC分类号： H03K19/173

    CPC分类号： H03K19/16 ,  G11C11/161 ,  H03K19/195

    摘要： This disclosure is directed to a magnetic logic device for implementing a combinational logic function. The magnetic logic device may include a chain of at least two magnetoresistive devices electrically coupled in series comprising a first terminal located at a first end of the chain and a second terminal located at a second end of the chain. The magnetic logic device may further include a voltage source configured to apply a voltage between the first terminal and the second terminal of the chain of at least two magnetoresistive devices electrically coupled in series. The magnetic logic device may further include a logic output generator configured to generate a logic output value for a logic function based on a magnitude of a current produced at the second terminal of the chain in response to the applied voltage.

    摘要翻译： 本公开涉及用于实现组合逻辑功能的磁逻辑器件。 磁逻辑器件可以包括串联电耦合的至少两个磁阻器件的链，包括位于链的第一端的第一端子和位于链的第二端的第二端子。 磁逻辑器件还可以包括电压源，其被配置为在串联电耦合的至少两个磁阻器件的链的第一端子和第二端子之间施加电压。 磁逻辑器件还可以包括逻辑输出发生器，其被配置为基于响应于所施加的电压在链的第二端产生的电流的大小来产生逻辑功能的逻辑输出值。