公开(公告)号：US20190042329A1

公开(公告)日：2019-02-07

申请号：US16024563

申请日：2018-06-29

Applicant: Utkarsh Y. Kakaiya ,  Pratik Marolia ,  Joshua David Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur ,  Yuling Yang ,  David Alexander Munday

Inventor： Utkarsh Y. Kakaiya ,  Pratik Marolia ,  Joshua David Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur ,  Yuling Yang ,  David Alexander Munday

IPC: G06F9/50 ,  G06F13/42

Abstract: A system is provided that includes a host processor coupled to a programmable acceleration coprocessor. The coprocessor may include logic for implementing a physical function and multiple associated virtual functions. The coprocessor may include a static programmable resource interface circuit (PIC) configured to perform management functions and one or more partial reconfiguration regions, each of which can be loaded with an accelerator function unit (AFU). An AFU may further be partitioned into AFU contexts (AFCs), each of which can be mapped to one of the virtual functions. The PIC enables hardware discovery/enumeration and loading of device drivers such that security isolation and interface performance are maintained.

公开(公告)号：US20210042254A1

公开(公告)日：2021-02-11

申请号：US17083200

申请日：2020-10-28

Applicant: Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

Inventor： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

IPC: G06F13/40 ,  G06F13/42

Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

公开(公告)号：US20190042801A1

公开(公告)日：2019-02-07

申请号：US16024022

申请日：2018-06-29

Applicant: JOSHUA FENDER ,  UTKARSH Y. KAKAIYA ,  MOHAN NAIR ,  BRIAN MORRIS ,  PRATIK MAROLIA

Inventor： JOSHUA FENDER ,  UTKARSH Y. KAKAIYA ,  MOHAN NAIR ,  BRIAN MORRIS ,  PRATIK MAROLIA

IPC: G06F21/76 ,  H04L29/08 ,  G06F21/54 ,  G06F11/14 ,  G06F1/32

Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

公开(公告)号：US20210004338A1

公开(公告)日：2021-01-07

申请号：US17026516

申请日：2020-09-21

Applicant: Pratik Marolia ,  Sanjay Kumar ,  Rajesh Sankaran ,  Utkarsh Y. Kakaiya

Inventor： Pratik Marolia ,  Sanjay Kumar ,  Rajesh Sankaran ,  Utkarsh Y. Kakaiya

IPC: G06F13/20 ,  G06F9/455 ,  G06F3/06

Abstract: Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID. IOV devices include multi-PASID helper devices and off-the-shelf devices such as NICs with modified ADIs to support C-PASID and D-PASID usage.