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公开(公告)号：US07626418B1
公开(公告)日：2009-12-01
申请号：US11803516
申请日：2007-05-14
IPC分类号： H03K19/177
CPC分类号： H03K19/17732
摘要： A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.
摘要翻译： 描述了用于集成电路的可配置接口。 集成电路包括第一核心，其中第一核心是外围组件互连Express（“PCIe”）接口设备的应用特定电路版本。 第一配置存储器单元与第一核相关联，并且第一配置存储单元用于配置第一核。 响应于配置比特流的第一部分，第一配置存储器单元是可编程的，并且配置比特流能够包括用于编程集成电路的可编程逻辑的用户逻辑信息。
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公开(公告)号：US07702840B1
公开(公告)日：2010-04-20
申请号：US11803556
申请日：2007-05-14
CPC分类号： H03K19/1737 , H03K19/17732 , H03K19/17744 , H03K19/17748 , H03K19/17792
摘要： Lane configuration of an interface device of an integrated circuit is described. A core is used to tile a portion of an integrated circuit with a first version of the core and a second version of the core. The core is an application specific circuit version of an interface device. The first version and the second version in combination have a sharable interface. Each of the first version and the second version has N lanes. The first version is a primary version and the second version is a secondary version responsive to a shared interface mode. The N lanes of the second version are combined with the N lanes of the first version via the sharable interface for providing 2-by-N lanes of input/output to the first version.
摘要翻译： 描述集成电路的接口装置的通道配置。 核心用于利用核心的第一版本和核心的第二版本来平铺集成电路的一部分。 核心是接口设备的应用电路版本。 第一个版本和第二个版本组合有一个共享的界面。 第一版和第二版都有N条通道。 第一个版本是主要版本，第二个版本是响应共享接口模式的辅助版本。 第二版本的N通道通过可共享接口与第一版本的N通道相结合，用于向第一版本提供输入/输出的2×N通道。
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