公开(公告)号：US08786310B1

公开(公告)日：2014-07-22

申请号：US13588647

申请日：2012-08-17

申请人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

发明人： Weiguang Lu ,  Paige A. Kolze ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Chen W. Tseng

IPC分类号： H01L25/00 ,  H03K19/173 ,  G06F7/38 ,  G06F17/50

CPC分类号： G06F7/38 ,  G06F17/5027 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/173 ,  H03K19/17756 ,  H03K19/1776 ,  H01L2924/00

摘要： Approaches for partially reconfiguring a frame are disclosed. In one approach, a circuit arrangement includes programmable resources, frames of configuration memory cells, and partial configuration control memory cells. Each frame includes a plurality of subsets of configuration memory cells, and each subset configures one of the programmable resources. Each partial configuration control memory cell is coupled to a respective one of the subsets. Responsive to a first partial bitstream that includes a quantity of configuration data for all the subsets of configuration cells of a first frame of the plurality of frames, each subset of the configuration memory cells of the first frame is configurable or not configurable responsive to the state of the associated partial configuration control memory cell.

摘要翻译： 公开了部分重新配置帧的方法。 在一种方法中，电路装置包括可编程资源，配置存储单元的帧和部分配置控制存储单元。 每个帧包括配置存储器单元的多个子集，并且每个子集配置可编程资源之一。 每个部分配置控制存储器单元耦合到相应的一个子集。 响应于第一部分比特流，其包括多个帧的第一帧的配置单元的所有子集的配置数据量，第一帧的配置存储器单元的每个子集可配置或不可配置，以响应于状态 的相关部分配置控制存储单元。

公开(公告)号：US6127845A

公开(公告)日：2000-10-03

申请号：US112700

申请日：1998-07-08

申请人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

发明人： Paige A. Kolze ,  Andre Stolmeijer ,  David D. Eaton

IPC分类号： H01L21/8234 ,  H01L27/118 ,  H01L25/00 ,  G06F7/38

CPC分类号： H01L21/823462 ,  H01L27/11807

摘要： In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second digital logic transistors the gates of which will not experience the programming voltage. The first digital logic transistors may be logic module input device transistors. The first digital logic transistors may be transistors coupled to an enable input lead where the enable input lead is couplable to a tie-high conductor or to a tie-low conductor depending on which of two antifuses is programmed.

摘要翻译： 在采用反熔丝的可编程器件中，其栅极经历编程电压Vpp的第一数字逻辑晶体管具有比其门不会经历编程电压的第二数字逻辑晶体管更大的栅绝缘体厚度。 第一数字逻辑晶体管可以是逻辑模块输入器件晶体管。 第一数字逻辑晶体管可以是耦合到使能输入引线的晶体管，其中根据两个反熔丝中的哪一个被编程，使能输入引线可以连接到连接导体或连接低导体。

公开(公告)号：US6018251A

公开(公告)日：2000-01-25

申请号：US931896

申请日：1997-09-17

申请人： Paige A. Kolze

发明人： Paige A. Kolze

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programmable integrated circuit (see FIG. 18) includes a plurality of interface cells with programmable antifuses disposed on a branch of a routing conductor. The routing conductor extends in a first direction and is coupled to one terminal of a programming transistor. The other terminal of the programming transistor is coupled to a programming driver via a programming conductor that extends in the first direction. The branch of the routing conductor crosses a plurality of routing wire segments of one of the interface cells, where programmable antifuses are disposed to couple the branch of the routing conductor to one or more of the routing wire segments. The routing wire segments extend parallel to one another in the first direction and are each coupled to a first terminal of separate programming transistors. The second terminals of the programming transistors are coupled to programming drivers via programming conductors that extend in a second direction, which is perpendicular to the first direction. Thus, the programming drivers for the routing wire segments and the routing conductor are positioned in different locations. Accordingly, when an antifuse is programming to couple the branch of the routing conductor with one of the routing wire segments, the two programming drivers are controlled by two different programming control shift registers.

摘要翻译： 可编程集成电路（参见图18）包括多个具有设置在布线导体的分支上的可编程反熔丝的接口单元。 布线导体沿第一方向延伸并且耦合到编程晶体管的一个端子。 编程晶体管的另一个端子通过在第一方向上延伸的编程导体耦合到编程驱动器。 布线导体的分支穿过接口单元之一的多个布线线段，其中设置可编程反熔丝以将布线导体的分支连接到一个或多个布线线段。 路由线段在第一方向上彼此平行延伸，并且各自耦合到单独编程晶体管的第一端。 编程晶体管的第二端子经由编程导体耦合到编程驱动器，编程导体在垂直于第一方向的第二方向上延伸。 因此，路由线段和路由导体的编程驱动器位于不同的位置。 因此，当反熔丝被编程以将布线导体的分支与布线线段中的一个耦合时，两个编程驱动器由两个不同的编程控制移位寄存器控制。

公开(公告)号：US07626418B1

公开(公告)日：2009-12-01

申请号：US11803516

申请日：2007-05-14

申请人： Paige A. Kolze ,  Laurent F. Stadler ,  Patrick C. McCarthy

发明人： Paige A. Kolze ,  Laurent F. Stadler ,  Patrick C. McCarthy

IPC分类号： H03K19/177

CPC分类号： H03K19/17732

摘要： A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.

摘要翻译： 描述了用于集成电路的可配置接口。 集成电路包括第一核心，其中第一核心是外围组件互连Express（“PCIe”）接口设备的应用特定电路版本。 第一配置存储器单元与第一核相关联，并且第一配置存储单元用于配置第一核。 响应于配置比特流的第一部分，第一配置存储器单元是可编程的，并且配置比特流能够包括用于编程集成电路的可编程逻辑的用户逻辑信息。

公开(公告)号：US6084428A

公开(公告)日：2000-07-04

申请号：US931897

申请日：1997-09-17

申请人： Paige A. Kolze ,  James A. Apland

发明人： Paige A. Kolze ,  James A. Apland

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A field programmable gate array has columns of logic modules. A programming conductor used to conduct programming current to program antifuses of the field programmable gate array extends between two adjacent columns of logic modules. First wire segments extend from the programming conductor and toward the logic modules of a first of the two adjacent columns. Second wire segments extend the opposite direction from the programming conductor and toward logic modules of the second of the two adjacent columns. Programming current used to program antifuses disposed along the first wire segments as well as antifuses disposed along the second wire segments can be supplied from the same programming conductor that extends between the two columns of logic modules. The logic modules of the first column are mirrored versions of the logic modules of the second column.

摘要翻译： 现场可编程门阵列具有逻辑模块列。 用于编程电流编程现场可编程门阵列的反熔丝的编程导体在两个相邻列的逻辑模块之间延伸。 第一线段从编程导体延伸到两个相邻列中的第一个的逻辑模块。 第二线段从编程导体向相反方向延伸，并且朝两个相邻列中的第二列的逻辑模块延伸。 用于编程沿着第一线段设置的反熔丝的编程电流以及沿着第二线段设置的反熔丝可以从在两列逻辑模块之间延伸的相同编程导体提供。 第一列的逻辑模块是第二列逻辑模块的镜像版本。

公开(公告)号：US5900742A

公开(公告)日：1999-05-04

申请号：US667783

申请日：1996-06-21

申请人： Paige A. Kolze ,  William D. Cox ,  Kevin K. Yee

发明人： Paige A. Kolze ,  William D. Cox ,  Kevin K. Yee

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/1778

摘要： An interface cell for a programmable integrated circuit includes a pad, an input buffer, a first routing conductor, a plurality of second routing conductors, and a plurality of antifuses. The input of the input buffer is coupled to the pad and the output of the input buffer is coupled to the first routing conductor so that an input signal from the pad can be supplied onto the first routing conductor without passing through any programmed antifuses. The second routing conductors extend parallel to one another in a direction perpendicular to the direction in which the first routing conductor extends. The second routing conductors cross the first routing conductor and then pass out of the interface cell and into a routing channel of the programmable integrated circuit. One of the antifuses is disposed at each location where one of the second routing conductors crosses the first routing conductor. Accordingly, an input signal from the pad can be supplied onto any desired one of the second routing conductors of the routing channel by programming only one antifuse. The interface cell contains an enablable register, the control inputs of which can be independently driven from any conductor in the adjacent routing channel. Combinatorial and registered outputs of the interface cell can be simultaneously routed to the routing channel and some interface cell outputs have 2.times. drive strength.

摘要翻译： 用于可编程集成电路的接口单元包括衬垫，输入缓冲器，第一布线导体，多个第二布线导体以及多个反熔丝。 输入缓冲器的输入耦合到焊盘，并且输入缓冲器的输出耦合到第一布线导体，使得来自焊盘的输入信号可以被提供到第一布线导体上，而不通过任何编程的反熔丝。 第二布线导体在垂直于第一布线导体延伸的方向的方向上彼此平行延伸。 第二路由导体穿过第一路由导体，然后从接口单元传出并进入可编程集成电路的路由信道。 一个反熔丝设置在每个位置，其中一个第二布线导体与第一布线导体交叉。 因此，通过仅编程一个反熔丝，可以将来自焊盘的输入信号提供给路由通道的任何所需的第二路由导体。 接口单元包含一个可用的寄存器，其控制输入可以独立地从相邻路由通道中的任何导体驱动。 接口单元的组合和注册输出可以同时路由到路由通道，一些接口单元输出具有2x驱动强度。

公开(公告)号：US5495181A

公开(公告)日：1996-02-27

申请号：US349093

申请日：1994-12-01

申请人： Paige A. Kolze

发明人： Paige A. Kolze

IPC分类号： G11C17/18 ,  H03K19/177

CPC分类号： G11C17/18

摘要： To facilitate the simultaneous programming of multiple antifuses on an integrated circuit, a first current path is established from a first programming terminal (VPP1) of a programmable logic device through a first antifuse to be programmed and a second current path is established from a second programming terminal (VPP2) of the programmable logic device through a second antifuse to be programmed. By supplying the programming current for programming the first antifuse from a different terminal than the programming current for programming the second antifuse, the two antifuses can be programmed simultaneously with an adequate amount of programming current being supplied to each antifuse. A programming current multiplexer circuit is disclosed for selectively coupling either a first programming voltage (VPP1) terminal, a second programming voltage (VPP2), or a ground terminal (GND) to a programming bus and/or to an antifuse to be programmed. The first and second current paths can be established using multiple such programming current multiplexer circuits.

摘要翻译： 为了便于在集成电路上同时对多个反熔丝进行编程，从可编程逻辑器件的第一编程端（VPP1）通过待编程的第一反熔丝建立第一电流路径，并且从第二编程建立第二电流路径 可编程逻辑器件的端子（VPP2）通过要编程的第二反熔丝。 通过提供用于编程来自不同于用于编程第二反熔丝的编程电流的不同端子的第一反熔丝的编程电流，可以在向每个反熔丝提供足够数量的编程电流的同时对两个反熔丝进行编程。 公开了一种编程电流多路复用器电路，用于将第一编程电压（VPP1）端子，第二编程电压（VPP2）或接地端子（GND））选择性地耦合到编程总线和/或将要编程的反熔丝。 可以使用多个这样的编程电流多路复用器电路来建立第一和第二电流路径。

公开(公告)号：US6130554A

公开(公告)日：2000-10-10

申请号：US932390

申请日：1997-09-17

申请人： Paige A. Kolze ,  Andrew K. Chan ,  James A. Apland

发明人： Paige A. Kolze ,  Andrew K. Chan ,  James A. Apland

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.

摘要翻译： 可编程集成电路（参见图13）包括多个路由资源，包括共线延伸的路由线段和用于测试路由线段完整性的测试电路。 路由资源结构包括布置在布线线段与多个晶体管之间的多个未编程的反熔丝，所述多个晶体管与相应的相应一个反熔丝电并联放置。 测试电路具有可以耦合到选择的一个路由资源结构以用于测试的公共节点。 在测试模式下，测试电路检测电流是否流过所选择的路由资源结构，并且响应于在输出节点上提供数字低值或数字高值。

公开(公告)号：US6081129A

公开(公告)日：2000-06-27

申请号：US931893

申请日：1997-09-17

申请人： James M. Apland ,  Paige A. Kolze

发明人： James M. Apland ,  Paige A. Kolze

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. To test the integrity of programming conductors, programming transistors, routing wire segments and a combinatorial portion of a logic module of the unprogrammed FPGA (see FIG. 16), a combination of digital logic values is supplied onto the inputs of the combinatorial portion in a test mode. A defect is determined to exist if the correct digital value is not then output by the combinatorial portion. The digital value output by the combinatorial portion is captured in the flip-flop of the logic module and is shifted out of the FPGA in a scan out test mode. A programming transistor, programming conductor and routing wire segment structure is also disclosed which facilitates such testing. In one embodiment (see FIG. 15), the gate of no programming transistor coupled to an output routing wire segment of the logic module (such as transistor 216) is permanently connected to the gate of any programming transistor coupled to an input routing wire segment of the logic module (such as transistors 200, 201 and 202).

摘要翻译： 公开了一种采用反熔丝的现场可编程门阵列（FPGA）的编程架构。 为了测试编程导体，编程晶体管，布线线段和未编程FPGA（参见图16）的逻辑模块的组合部分的完整性，数字逻辑值的组合被提供到组合部分的输入端 测试模式。 如果正确的数字值不由组合部分输出，则确定存在缺陷。 由组合部分输出的数字值被捕获在逻辑模块的触发器中，并以扫描输出测试模式从FPGA中移出。 还公开了编程晶体管，编程导体和布线线段结构，其有助于这种测试。 在一个实施例中（参见图15），耦合到逻辑模块（例如晶体管216）的输出布线线段的无编程晶体管的栅极永久连接到耦合到输入布线线段的任何编程晶体管的栅极 的逻辑模块（例如晶体管200,201和202）。

公开(公告)号：US5825201A

公开(公告)日：1998-10-20

申请号：US667702

申请日：1996-06-21

申请人： Paige A. Kolze

发明人： Paige A. Kolze

IPC分类号： H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. In one aspect, the number of programming conductors and the number of perpendicular programming control conductors for a logic module are substantially equal. In another aspect, programming current is supplied onto long routing wire segments via two programming transistors and two programming conductors. In another aspect, a pattern of programming drivers alternates from one side of the integrated circuit to the opposite side from one column of macrocells to the next. In other aspects, control conductors and programming conductors are tested with test antifuses and test transistors. In another aspect, adjacent logic modules have mirrored structures so that they can share an intervening programming conductor resource. In another aspect, L-shaped programming power busses are provided and in another aspect, an express wire is simultaneously driven with programming current from two different programming voltage terminals. In other aspects, a test circuit tests the integrity of collinear routing wire segments and output programming transistors are tested. In another aspect, antifuses on branches of clock conductors are programmed.

摘要翻译： 公开了一种采用反熔丝的现场可编程门阵列（FPGA）的编程架构。 在一个方面，逻辑模块的编程导体的数量和垂直编程控制导体的数量基本相等。 在另一方面，通过两个编程晶体管和两个编程导体将编程电流提供给长路由线段。 在另一方面，编程驱动器的模式从集成电路的一侧交替到从一列宏单元到另一列的相反侧。 在其他方面，使用测试反熔丝和测试晶体管测试控制导体和编程导体。 在另一方面，相邻逻辑模块具有镜像结构，使得它们可以共享中间编程导体资源。 在另一方面，提供L形编程功率总线，并且在另一方面，快速导线由来自两个不同编程电压端子的编程电流同时驱动。 在其他方面，测试电路测试共线路由线段的完整性，并对输出编程晶体管进行测试。 在另一方面，编程时钟导体的分支上的反熔丝。