公开(公告)号：US08125835B2

公开(公告)日：2012-02-28

申请号：US12343658

申请日：2008-12-24

申请人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Raghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan I. Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

发明人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Raghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan I. Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/14 ,  G11C5/145 ,  G11C16/06 ,  G11C16/12 ,  G11C16/28 ,  G11C16/32

摘要： In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

摘要翻译： 在这里描述的实施例中，存储器架构具有非易失性存储器单元阵列和一对独立控制的电压泵。 该对电压泵被耦合以在编程和擦除操作期间将正和负电压偏压提供给存储器阵列，使得正和负电压偏置的幅度之和被施加在存取存储器单元的存储节点上 。

公开(公告)号：US20100074028A1

公开(公告)日：2010-03-25

申请号：US12343658

申请日：2008-12-24

申请人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Raghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan I. Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

发明人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Raghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan I. Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/14 ,  G11C5/145 ,  G11C16/06 ,  G11C16/12 ,  G11C16/28 ,  G11C16/32

摘要： In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

摘要翻译： 在这里描述的实施例中，存储器架构具有非易失性存储器单元阵列和一对独立控制的电压泵。 该对电压泵被耦合以在编程和擦除操作期间将正和负电压偏压提供给存储器阵列，使得正和负电压偏置的幅度之和被施加在存取存储器单元的存储节点上 。

公开(公告)号：US20120188826A1

公开(公告)日：2012-07-26

申请号：US13407660

申请日：2012-02-28

申请人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Raghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan I. Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

发明人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Raghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan I. Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C5/145 ,  G11C16/06 ,  G11C16/12 ,  G11C16/28 ,  G11C16/32

摘要： In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

摘要翻译： 在这里描述的实施例中，存储器架构具有非易失性存储器单元阵列和一对独立控制的电压泵。 该对电压泵被耦合以在编程和擦除操作期间将正和负电压偏压提供给存储器阵列，使得正和负电压偏置的幅度之和被施加在存取存储器单元的存储节点上 。

公开(公告)号：US08542541B2

公开(公告)日：2013-09-24

申请号：US13407660

申请日：2012-02-28

申请人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Srinivasaraghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

发明人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Srinivasaraghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C5/145 ,  G11C16/06 ,  G11C16/12 ,  G11C16/28 ,  G11C16/32

摘要： In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

摘要翻译： 在这里描述的实施例中，存储器架构具有非易失性存储器单元阵列和一对独立控制的电压泵。 该对电压泵被耦合以在编程和擦除操作期间将正和负电压偏压提供给存储器阵列，使得正和负电压偏置的幅度之和被施加在存取存储器单元的存储节点上 。

公开(公告)号：US07969804B1

公开(公告)日：2011-06-28

申请号：US12343617

申请日：2008-12-24

申请人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Srinivasaraghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

发明人： Ryan T. Hirose ,  Fredrick Jenne ,  Vijay Srinivasaraghavan ,  Igor G. Kouznetsov ,  Paul Fredrick Ruths ,  Cristinel Zonte ,  Bogdan Georgescu ,  Leonard Vasile Gitlan ,  James Paul Myers

IPC分类号： G11C7/00

CPC分类号： G11C16/14 ,  G11C5/145 ,  G11C16/06 ,  G11C16/12 ,  G11C16/28 ,  G11C16/32

摘要： A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.

摘要翻译： 存储器架构具有布置成行和列的非易失性存储器单元的阵列，以及耦合到阵列内的至少一列的读出放大器，用于感测存储在非易失性存储单元之一内的数据位。 为了提供精确的感测，提供参考电流发生器并耦合到读出放大器。 参考电流发生器提供具有可调幅度和可调斜率的第一参考电流，以及具有可调幅度但恒定斜率的第二参考电流。 第一个参考电流被提供给感测放大器，用于感测数据位。 第二参考电流被提供给用于产生用于控制读出放大器时序的时钟信号的控制块。