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    Two mask floating gate EEPROM and method of making
    6.
    发明授权
    Two mask floating gate EEPROM and method of making 失效
    两个掩模浮栅EEPROM及其制作方法

    公开(公告)号：US06897514B2

    公开(公告)日：2005-05-24

    申请号：US10066376

    申请日：2002-02-05

    申请人： Igor G. Kouznetsov ,  Andrew J. Walker

    发明人： Igor G. Kouznetsov ,  Andrew J. Walker

    IPC分类号： H01L27/06 ,  H01L27/112 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/76

    CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/12 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/8616

    摘要： There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.

    摘要翻译： 提供了诸如EEPROM晶体管的浮动栅极晶体管，以及使用两个掩模步骤制造晶体管的方法。 制造晶体管的方法包括使用第一光致抗蚀剂掩模图案化浮栅，以形成浮栅，并且使用浮置栅极作为掩模掺杂有源区，以在有源区中形成源区和漏区。 该方法还包括使用第二光致抗蚀剂掩模来形成控制栅极层，控制栅极介电层，浮动栅极轨道，隧道介电层和有源区域以形成控制栅极，控制栅极电介质，浮动栅极， 隧道电介质和沟道岛区。

    Anti-fuse memory cell with asymmetric breakdown voltage
    9.
    发明授权
    Anti-fuse memory cell with asymmetric breakdown voltage 有权
    具有不对称击穿电压的反熔丝存储单元

    公开(公告)号：US06704235B2

    公开(公告)日：2004-03-09

    申请号：US10027466

    申请日：2001-12-20

    申请人： N. Johan Knall ,  James M. Cleeves ,  Igor G. Kouznetsov ,  Michael A. Vyvoda

    发明人： N. Johan Knall ,  James M. Cleeves ,  Igor G. Kouznetsov ,  Michael A. Vyvoda

    IPC分类号： H01L2904

    CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 Å and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic. The antifuse layer is formed of an antifuse material characterized by a thickness Tminlife at which the antifuse material is ruptured by a minimum number of write pulses having a polarity that reverse biases diode components included in the memory cell. The average thickness T of the antifuse layer is less than the thickness Tminlife.

    摘要翻译： 用于二维或三维存储器阵列的存储单元包括位于导体之间的第一和第二导体和一组层。 这组层包括厚度小于35A的电介质破裂抗熔丝层和在2V时大于1mA / cm 2的漏电流密度（在未破裂状态下）。这种低厚度和高电流泄漏 密度提供具有不对称介电层击穿电压特性的存储单元。 反熔丝层由反熔丝材料形成，其特征在于厚度Tminmin，其中反熔丝材料被最小数量的具有反向偏置存储单元中包含的二极管组件的极性的写入脉冲破裂。 反熔丝层的平均厚度T小于厚度Tminlife。