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1.
公开(公告)号:US06645812B2
公开(公告)日:2003-11-11
申请号:US10033949
申请日:2001-12-28
申请人: Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
发明人: Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
IPC分类号: H01L21336
CPC分类号: H01L29/66825 , H01L29/7883
摘要: A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.
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公开(公告)号:US06654281B2
公开(公告)日:2003-11-25
申请号:US10177884
申请日:2002-06-20
申请人: Georg Georgakos , Kai Huckels , Jakob Kriz , Christoph Kutter , Andreas Liebelt , Christoph Ludwig , Elard Stein von Kamienski , Peter Wawer
发明人: Georg Georgakos , Kai Huckels , Jakob Kriz , Christoph Kutter , Andreas Liebelt , Christoph Ludwig , Elard Stein von Kamienski , Peter Wawer
IPC分类号: G11C1604
CPC分类号: H01L27/11519 , G11C16/0416 , H01L27/11521
摘要: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.
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公开(公告)号:US06368970B1
公开(公告)日:2002-04-09
申请号:US09645238
申请日:2000-08-24
申请人: Ayad Abdul-Hak , Achim Gratz , Christoph Ludwig , Reinhold Rennekamp , Elard Stein Von Kamienski , Peter Wawer
发明人: Ayad Abdul-Hak , Achim Gratz , Christoph Ludwig , Reinhold Rennekamp , Elard Stein Von Kamienski , Peter Wawer
IPC分类号: H01L21302
CPC分类号: H01L21/76232 , H01L21/823481
摘要: A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.
摘要翻译: 一种制造半导体结构的方法包括以下步骤:提供半导体衬底,在半导体衬底上提供缓冲氧化物层,并在缓冲氧化物层上提供硬掩模。 通过使用硬掩模蚀刻STI沟槽,并且在STI沟槽中提供衬垫氧化物层。 去除硬掩模以暴露缓冲氧化物层,并通过蚀刻工艺除去缓冲氧化物层。 在蚀刻工艺中,缓冲氧化物层比衬垫氧化物层蚀刻得更快。 在半导体衬底上设置栅氧化层。 还提供半导体配置。
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