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    Semiconductor configuration and corresponding production process
    2.
    发明授权
    Semiconductor configuration and corresponding production process 有权
    半导体配置及相应的生产工艺

    公开(公告)号：US06368970B1

    公开(公告)日：2002-04-09

    申请号：US09645238

    申请日：2000-08-24

    申请人： Ayad Abdul-Hak ,  Achim Gratz ,  Christoph Ludwig ,  Reinhold Rennekamp ,  Elard Stein Von Kamienski ,  Peter Wawer

    发明人： Ayad Abdul-Hak ,  Achim Gratz ,  Christoph Ludwig ,  Reinhold Rennekamp ,  Elard Stein Von Kamienski ,  Peter Wawer

    IPC分类号： H01L21302

    CPC分类号： H01L21/76232 ,  H01L21/823481

    摘要： A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.

    摘要翻译： 一种制造半导体结构的方法包括以下步骤：提供半导体衬底，在半导体衬底上提供缓冲氧化物层，并在缓冲氧化物层上提供硬掩模。 通过使用硬掩模蚀刻STI沟槽，并且在STI沟槽中提供衬垫氧化物层。 去除硬掩模以暴露缓冲氧化物层，并通过蚀刻工艺除去缓冲氧化物层。 在蚀刻工艺中，缓冲氧化物层比衬垫氧化物层蚀刻得更快。 在半导体衬底上设置栅氧化层。 还提供半导体配置。

    Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts
    4.
    发明授权
    Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts 失效
    用于在存储单元阵列中提供位线触点的方法和具有位线触点的存储单元阵列

    公开(公告)号：US07008849B2

    公开(公告)日：2006-03-07

    申请号：US10724903

    申请日：2003-12-01

    申请人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

    发明人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

    IPC分类号： H01L21/8236

    CPC分类号： H01L27/11568 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/112

    摘要： A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.

    摘要翻译： 一种用于在存储单元阵列中提供位线触点的方法包括沿第一方向布置的多个位线，位线由绝缘层覆盖，多个字线沿垂直于位线上方的第一方向的第二方向布置，以及 位于位线和字线彼此交叉的点处的存储单元。 根据本发明的第一方面，在未被字线覆盖的部分处，从位线移除隔离层，而位线之间的区域保持不受影响。 或者，从整个电池阵列中去除绝缘层。 然后，在位线的露出部分上设置导电材料。 该方法用于在氮化物只读存储器（NROM TM））芯片中提供位线触点。

    Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells
    5.
    发明授权
    Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells 失效
    用于包含非易失性半导体存储单元的存储单元阵列的少数载波宿

    公开(公告)号：US07755130B2

    公开(公告)日：2010-07-13

    申请号：US11747037

    申请日：2007-05-10

    申请人： Elard Stein Von Kamienski

    发明人： Elard Stein Von Kamienski

    IPC分类号： H01L29/94

    CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/32 ,  H01L29/66833

    摘要： A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body.

    摘要翻译： 规定了非易失性半导体存储单元的存储单元阵列，其中在存储单元阵列的区域内在半导体本体内形成少数载流子阱，少数载流子排布置在形成于半导体本体中的空间电荷区结构之外 在与半导体本体的表面一样远的半导体区域的情况下，半导体存储单元的工作期间和少数载流子阱具有较短的少数载流子寿命。

    MINORITY CARRIER SINK FOR A MEMORY CELL ARRAY COMPRISING NONVOLATILE SEMICONDUCTOR MEMORY CELLS
    6.
    发明申请
    MINORITY CARRIER SINK FOR A MEMORY CELL ARRAY COMPRISING NONVOLATILE SEMICONDUCTOR MEMORY CELLS 失效
    用于包含非易失性半导体存储器单元的存储器阵列的少量载体

    公开(公告)号：US20080277717A1

    公开(公告)日：2008-11-13

    申请号：US11747037

    申请日：2007-05-10

    申请人： Elard Stein Von Kamienski

    发明人： Elard Stein Von Kamienski

    IPC分类号： H01L27/088

    CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/32 ,  H01L29/66833

    摘要： A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body.

    摘要翻译： 规定了非易失性半导体存储单元的存储单元阵列，其中在存储单元阵列的区域内在半导体本体内形成少数载流子阱，少数载流子排布置在形成于半导体本体中的空间电荷区结构之外 在与半导体本体的表面一样远的半导体区域的情况下，半导体存储单元的工作期间和少数载流子阱具有较短的少数载流子寿命。