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1.发明授权公开(公告)号：US07122434B2
公开(公告)日：2006-10-17
申请号：US11124726
申请日：2005-05-09
IPC分类号： H01L21/8234
CPC分类号： H01L27/115 , H01L21/76897 , H01L23/522 , H01L23/528 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.
摘要翻译： 半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道 导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于 每个第一轨道导体303和位于其上方的对应的第三轨道导体307之间的电接触305。
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2.发明授权公开(公告)号：US06645812B2
公开(公告)日：2003-11-11
申请号：US10033949
申请日：2001-12-28
申请人： Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
发明人： Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/7883
摘要： A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.
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3.发明申请公开(公告)号：US20050201131A1
公开(公告)日：2005-09-15
申请号：US11124726
申请日：2005-05-09
IPC分类号： H01L21/60 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/02 , G11C11/42
CPC分类号： H01L27/115 , H01L21/76897 , H01L23/522 , H01L23/528 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.
摘要翻译： 半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道 导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于 每个第一轨道导体303和位于其上方的对应的第三轨道导体307之间的电接触305。
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公开(公告)号：US06531359B1
公开(公告)日：2003-03-11
申请号：US09596420
申请日：2000-06-19
申请人： Georg Tempel , Christoph Kutter
发明人： Georg Tempel , Christoph Kutter
IPC分类号： H01L21336
CPC分类号： H01L27/11517
摘要： A method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, includes burying insulation zones on a silicon substrate in accordance with an STI (Shallow Trench Isolation) technique, forming word lines on the insulation zones, covering the word lines with a hard mask and side wall oxides and CVD depositing an oxide or nitride laterally onto the hard mask and onto the side wall oxides to define a spacer. Spacer channels are etched into the insulation zones between adjoining word lines. An SAS (Self Aligned Source) resist mask is applied to mask each two adjacent coated word lines on mutually facing sections, including the spacer channel located between these word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked on mutually facing sections. The SAS resist mask is exposed. Those regions of the insulation zones which are not covered by the SAS perforated mask are anisotropic etched, with a bottom of uncovered spacer channels being lowered down at least to a surface of the uncovered silicon substrate. The SAS perforated mask is removed to uncover a resultant structure.
摘要翻译： 一种用于制造存储单元阵列，特别是EPROM或EEPROM存储单元阵列的方法，包括根据STI（浅沟槽隔离）技术在硅衬底上埋设绝缘区，在绝缘区上形成字线，覆盖字 具有硬掩模和侧壁氧化物的线和CVD将氧化物或氮化物横向沉积到硬掩模上并到侧壁氧化物上以限定间隔物。 间隔通道被蚀刻到相邻字线之间的绝缘区域中。 应用SAS（自对准源）抗蚀剂掩模来掩蔽相互面对的部分上的每两个相邻涂覆的字线，包括位于这些字线之间的间隔通道，而掩蔽的字线对的每两个相邻的被掩蔽的字线保持相互掩蔽 面向部分。 SAS抗蚀剂掩模露出。 未被SAS穿孔掩模覆盖的绝缘区域的那些区域是各向异性蚀刻的，未覆盖的间隔物通道的底部至少下降至未覆盖的硅衬底的表面。 移除SAS穿孔的面罩以露出所得到的结构。
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5.发明申请公开(公告)号：US20110227204A1
公开(公告)日：2011-09-22
申请号：US13152971
申请日：2011-06-03
IPC分类号： H01L23/495 , H01L21/786 , H01L21/60
CPC分类号： H01L24/14 , H01L21/568 , H01L21/6835 , H01L23/12 , H01L23/48 , H01L23/50 , H01L23/5381 , H01L23/5389 , H01L24/06 , H01L24/19 , H01L24/96 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/92 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01068 , H01L2924/014 , H01L2924/15174 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/181 , H01L2924/19015 , H01L2924/19042 , H01L2924/19104 , H01L2224/96 , H01L2224/82 , H01L2924/00
摘要： A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body.
摘要翻译： 半导体器件包括：半导体芯片，包括第一导电元件;以及第二导电元件，其布置在半导体芯片外部，并在第一位置处电连接到第一导电元件。 还包括布置在半导体芯片外部并在第二位置与第一导电元件电连接的第三导电元件和布置在半导体芯片外部的第四导电元件。 封装体封装半导体芯片。 芯片上的第四导电元件的垂直投影在第一位置与第二位置之间穿过第一导电元件。 第二导电元件，第三导电元件和第四导电元件中的至少一个在半导体芯片和封装体上延伸。
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6.发明申请公开(公告)号：US20090166843A1
公开(公告)日：2009-07-02
申请号：US11965081
申请日：2007-12-27
IPC分类号： H01L23/485
CPC分类号： H01L24/14 , H01L21/568 , H01L21/6835 , H01L23/12 , H01L23/48 , H01L23/50 , H01L23/5381 , H01L23/5389 , H01L24/06 , H01L24/19 , H01L24/96 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/92 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01068 , H01L2924/014 , H01L2924/15174 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/181 , H01L2924/19015 , H01L2924/19042 , H01L2924/19104 , H01L2224/96 , H01L2224/82 , H01L2924/00
摘要： A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location.
摘要翻译： 半导体器件包括：半导体芯片，包括第一导电元件;以及第二导电元件，其布置在半导体芯片外部，并在第一位置处电连接到第一导电元件。 还包括布置在半导体芯片外部并在第二位置与第一导电元件电连接的第三导电元件和布置在半导体芯片外部的第四导电元件。 芯片上的第四导电元件的垂直投影在第一位置与第二位置之间穿过第一导电元件。
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7.发明授权Semiconductor structure having buried track conductors, and method for generating an electrical contact with buried track conductors 失效具有掩埋轨道导体的半导体结构，以及用于产生与掩埋轨道导体的电接触的方法公开(公告)号：US06909153B2
公开(公告)日：2005-06-21
申请号：US10159859
申请日：2002-05-31
IPC分类号： H01L21/60 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/115 , H01L21/76897 , H01L23/522 , H01L23/528 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.
摘要翻译： 半导体结构300包括多个第一轨道导体303，多个第二轨道导体304，其相对于第一轨道导体303绝缘并与这些第一轨道导体303一起形成栅格，以及多个第三轨道 导体307平行于第一轨道导体303之上，第三轨道导体307部分地覆盖第二轨道导体304并相对于其彼此绝缘，其中半导体结构300在每种情况下在两个相邻的第二轨道导体304之间位于 每个第一轨道导体303和位于其上方的相应的第三轨道导体307之间的电接触305。
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公开(公告)号：US06654281B2
公开(公告)日：2003-11-25
申请号：US10177884
申请日：2002-06-20
申请人： Georg Georgakos , Kai Huckels , Jakob Kriz , Christoph Kutter , Andreas Liebelt , Christoph Ludwig , Elard Stein von Kamienski , Peter Wawer
发明人： Georg Georgakos , Kai Huckels , Jakob Kriz , Christoph Kutter , Andreas Liebelt , Christoph Ludwig , Elard Stein von Kamienski , Peter Wawer
IPC分类号： G11C1604
CPC分类号： H01L27/11519 , G11C16/0416 , H01L27/11521
摘要： A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.
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公开(公告)号：US5943255A
公开(公告)日：1999-08-24
申请号：US49558
申请日：1998-03-27
申请人： Christoph Kutter , Georg Tempel
发明人： Christoph Kutter , Georg Tempel
IPC分类号： G11C17/10 , H01L27/112 , G11C17/00 , G11C11/34 , G11C11/50
CPC分类号： G11C17/10 , H01L27/112
摘要： The read only memory has a plurality of conductor track planes one above the other. The conductor tracks in adjacent planes are oriented such that they intersect in intersecting regions. In these intersecting regions, either a VIA tunnel contact is provided, which represents a logic "1" or no VIA tunnel contact is provided, so that this intersecting region represents a logic "0". In this way, over the same surface area, a plurality of memory cells can be produced one above the other. The read only memory is produced with a defined sequence of process steps and it is operated by selectively applying predetermined voltages across the various conductor tracks.
摘要翻译： 只读存储器具有多个导体轨道平面，一个在另一个之上。 相邻平面中的导体轨迹定向成使得它们在交叉区域相交。 在这些相交区域中，提供VIA隧道触点，其表示逻辑“1”或不提供VIA隧道触点，使得该相交区域表示逻辑“0”。 以这种方式，在相同的表面积上，可以彼此重复地制造多个存储单元。 只读存储器以规定的处理步骤顺序产生，并且通过选择性地在各种导体轨道上施加预定电压来操作该只读存储器。
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