公开(公告)号：US20070245279A1

公开(公告)日：2007-10-18

申请号：US11279312

申请日：2006-04-11

申请人： Vikas Agarwal ,  Michael Hyeok Lee ,  Philip Shephard

发明人： Vikas Agarwal ,  Michael Hyeok Lee ,  Philip Shephard

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and system for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.

摘要翻译： 通过模拟全阵列模型中的边缘单元的操作来验证阵列的性能的方法和系统减少了完整设计验证所需的计算时间。 阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。 如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。 观察到字线到达以确定最坏情况行进行选择。 对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。 对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。

公开(公告)号：US20060176731A1

公开(公告)日：2006-08-10

申请号：US11055043

申请日：2005-02-10

申请人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

发明人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

IPC分类号： G11C11/00

CPC分类号： G11C29/1201 ,  G11C11/41 ,  G11C11/419 ,  G11C29/12

摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode, while preventing other data bits of “X” state from entering the latch circuit. A second enabling circuit enables the data hold circuit to receive data bits from a self test source in place of respective data bits from the SRAM array that are prevented from entering the latch circuit.

摘要翻译： 提供了将单个锁存电路中的自检和功能特征组合在一起的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L 1 -L 2锁存器。 在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。 在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。 锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。 响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位 写模式，同时防止“X”状态的其他数据位进入锁存电路。 第二启用电路使得数据保持电路能够从自检源代替来自SRAM阵列的相应数据位，以防止其进入锁存电路。

公开(公告)号：US20070234253A1

公开(公告)日：2007-10-04

申请号：US11391880

申请日：2006-03-29

申请人： Jeffrey Soreff ,  Philip Shephard ,  Fred Yang ,  Vasant Rao

发明人： Jeffrey Soreff ,  Philip Shephard ,  Fred Yang ,  Vasant Rao

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a system for building static models for transistor circuit design is described. This method includes performing an automatic timing model construction several times on certain problem CCCs, with different, typically incompatible sets of user-selected local information for each call. Each of the sets of local information is considered a mode of operation of the circuit, each generating a timing model for the mode of operation. The resulting set of timing models are placed in parallel in the overall timing graph for the digital design as a whole, which has the effect of making the timing analysis choose the most conservative numbers from across the set of parallel models.

摘要翻译： 描述了一种用于构建晶体管电路设计的静态模型的方法和系统。 该方法包括在某些问题CCC上执行多次自动定时模型构造，其中每个呼叫具有不同的，通常不兼容的用户选择的本地信息的集合。 每组本地信息被认为是电路的操作模式，每一个都产生用于操作模式的定时模型。 所得到的定时模型集合在整个数字设计的整体时序图中并行放置，这具有使得时序分析从整个并行模型集合中选择最保守的数字的效果。