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    METHODS AND SYSTEMS FOR LOCALLY GENERATING NON-INTEGRAL DIVIDED CLOCKS WITH CENTRALIZED STATE MACHINES
    2.
    发明申请
    METHODS AND SYSTEMS FOR LOCALLY GENERATING NON-INTEGRAL DIVIDED CLOCKS WITH CENTRALIZED STATE MACHINES 失效
    用集中式状态机定位生成非整体分时钟的方法与系统

    公开(公告)号：US20070176653A1

    公开(公告)日：2007-08-02

    申请号：US11419224

    申请日：2006-05-19

    申请人： William Huott ,  Charlie Hwang ,  Timothy McNamara

    发明人： William Huott ,  Charlie Hwang ,  Timothy McNamara

    IPC分类号： H03K23/00

    CPC分类号： G06F7/68 ,  H03K23/68

    摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

    摘要翻译： 用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。 集中式状态机包括响应于非整数数量的全局时钟周期的整个周期的计数器，状态机响应于计数器产生控制信号。 控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低电平信号。 响应于全局时钟信号，时钟高电平信号和时钟低电平信号，本地通道门产生（n + 0.5）至1时钟信号。

    MULTIFUNCTIONAL LATCH CIRCUIT FOR USE WITH BOTH SRAM ARRAY AND SELF TEST DEVICE
    3.
    发明申请
    MULTIFUNCTIONAL LATCH CIRCUIT FOR USE WITH BOTH SRAM ARRAY AND SELF TEST DEVICE 失效
    具有两个SRAM阵列和自检测试器件的多功能锁存电路

    公开(公告)号：US20060176731A1

    公开(公告)日：2006-08-10

    申请号：US11055043

    申请日：2005-02-10

    申请人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

    发明人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

    IPC分类号： G11C11/00

    CPC分类号： G11C29/1201 ,  G11C11/41 ,  G11C11/419 ,  G11C29/12

    摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode, while preventing other data bits of “X” state from entering the latch circuit. A second enabling circuit enables the data hold circuit to receive data bits from a self test source in place of respective data bits from the SRAM array that are prevented from entering the latch circuit.

    摘要翻译： 提供了将单个锁存电路中的自检和功能特征组合在一起的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L 1 -L 2锁存器。 在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。 在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。 锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。 响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位 写模式，同时防止“X”状态的其他数据位进入锁存电路。 第二启用电路使得数据保持电路能够从自检源代替来自SRAM阵列的相应数据位，以防止其进入锁存电路。

    METHODS AND APPARATUS FOR DEFECT ISOLATION
    4.
    发明申请
    METHODS AND APPARATUS FOR DEFECT ISOLATION 失效
    缺陷分离方法与装置

    公开(公告)号：US20050193297A1

    公开(公告)日：2005-09-01

    申请号：US10708380

    申请日：2004-02-27

    申请人： Leendert Huisman ,  William Huott ,  Maroun Kassab ,  Franco Motika

    发明人： Leendert Huisman ,  William Huott ,  Maroun Kassab ,  Franco Motika

    IPC分类号： G01R31/28 ,  G01R31/3185

    CPC分类号： G01R31/318533

    摘要： In a first aspect, a first method is provided for isolating a defect in a scan chain. The first method includes the steps of (1) modifying a first test mode of one or more of a plurality of latches included in the scan chain; (2) operating the one or more latches whose first test modes are modified in the modified first test mode; and (3) operating one or more of the plurality of latches included in the scan chain in a second test mode. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了用于隔离扫描链中的缺陷的第一方法。 第一种方法包括以下步骤：（1）修改包括在扫描链中的多个锁存器中的一个或多个的第一测试模式; （2）在修改后的第一测试模式下操作其第一测试模式被修改的一个或多个锁存器; 以及（3）在第二测试模式中操作包括在扫描链中的多个锁存器中的一个或多个。 提供了许多其他方面。

    Self test method and apparatus for identifying partially defective memory
    6.
    发明申请
    Self test method and apparatus for identifying partially defective memory 失效
    用于识别部分缺陷记忆的自检方法和装置

    公开(公告)号：US20060156130A1

    公开(公告)日：2006-07-13

    申请号：US11008371

    申请日：2004-12-09

    申请人： William Huott ,  David Lund ,  Kenneth Marz ,  Bryan Mechtly ,  Pradip Patel

    发明人： William Huott ,  David Lund ,  Kenneth Marz ,  Bryan Mechtly ,  Pradip Patel

    IPC分类号： G01R31/28

    CPC分类号： G06F12/0802 ,  G06F12/126 ,  G11C29/44 ,  G11C29/88 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/4402

    摘要： A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.

    摘要翻译： 提供了一种包括具有高速缓存存储器的处理器的计算系统。 高速缓冲存储器包括多个可独立配置的子部分，每个细分包括存储器阵列。 计算系统的服务元素（SE）可操作以执行内置自检（BIST）以测试高速缓冲存储器，BIST可操作以确定任何子细分是否有缺陷。 当确定由BIST确定为有缺陷的高速缓冲存储器的一个细分是不可修复时，SE从系统配置逻辑地删除缺陷细分，并且SE可操作以允许处理器在没有逻辑删除的情况下操作 细分。 当有多个缺陷细分超过阈值时，SE还可操作以确定处理器有缺陷。

    METHODS AND APPARATUS FOR TESTING A SCAN CHAIN TO ISOLATE DEFECTS
    8.
    发明申请
    METHODS AND APPARATUS FOR TESTING A SCAN CHAIN TO ISOLATE DEFECTS 失效
    用于测试扫描链以分离缺陷的方法和装置

    公开(公告)号：US20080059857A1

    公开(公告)日：2008-03-06

    申请号：US11924597

    申请日：2007-10-25

    申请人： LEENDERT HUISMAN ,  William Huott ,  Maroun Kassab ,  Franco Motika

    发明人： LEENDERT HUISMAN ,  William Huott ,  Maroun Kassab ,  Franco Motika

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318533

    摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

    摘要翻译： 提供了用于隔离扫描链中的缺陷的系统，方法和装置。 本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。 扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值， 到了错误。 这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。 提供了许多其他方面。

    Circuits for locally generating non-integral divided clocks with centralized state machines
    9.
    发明申请
    Circuits for locally generating non-integral divided clocks with centralized state machines 失效
    用集中式状态机本地生成非积分分时钟的电路

    公开(公告)号：US20070176651A1

    公开(公告)日：2007-08-02

    申请号：US11341032

    申请日：2006-01-27

    申请人： William Huott ,  Charlie Hwang ,  Timothy McNamara

    发明人： William Huott ,  Charlie Hwang ,  Timothy McNamara

    IPC分类号： H03K23/00

    CPC分类号： H03K23/502

    摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to−1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

    摘要翻译： 用于在芯片上本地生成比率时钟的电路。 该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。 状态机包括响应于非整数个全局时钟周期的整个周期的计数器。 状态机响应于计数器产生控制信号。 分段锁存器接收控制信号并产生时钟高信号和时钟低信号，时钟高信号和时钟低信号具有从目标分频比时钟的波形导出的模式，时钟高信号和时钟低信号具有 符合目标分频时钟频率和占空比的模式。 本地通过门接收时钟低电平信号和时钟高电平信号，并响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。