公开(公告)号：US5450363A

公开(公告)日：1995-09-12

申请号：US252750

申请日：1994-06-02

申请人： Mark Christopherson ,  Phillip M. Kwong ,  Steven E. Wells

发明人： Mark Christopherson ,  Phillip M. Kwong ,  Steven E. Wells

IPC分类号： G06F11/10 ,  G11C11/56 ,  G11C7/00

CPC分类号： G11C11/56 ,  G06F11/1072 ,  G11C29/00

摘要： A memory system contains a plurality of memory cells, a sensing circuit, and a translator circuit. The memory cells store one of a plurality of threshold levels, wherein the threshold levels demarcate windows for designating more than a single bit of data for each memory cell. The sensing circuit, coupled to the memory cells, generates at least one binary coded bit from the threshold level sensed. A translator circuit translates the binary coded bits to gray coded bits such that only one bit changes state between adjacent threshold levels. Because of this, a decrease from one threshold level to a lower adjacent threshold level in a memory cell results in the change of only a single bit of data, thus improving the memory system reliability. The memory system also includes the ability to store threshold states in either a multi-level cell mode or a standard level cell mode. In the standard cell mode, the translator circuit directly passes the binary coded bits without performing any translation.

摘要翻译： 存储器系统包含多个存储器单元，感测电路和转换器电路。 所述存储器单元存储多个阈值电平中的一个，其中所述阈值电平划分用于为每个存储单元指定多于一位数据的窗口的窗口。 耦合到存储器单元的感测电路从感测到的阈值电平产生至少一个二进制编码位。 转换器电路将二进制编码比特转换为灰度编码比特，使得只有一个比特在相邻阈值水平之间改变状态。 因此，存储器单元中从一个阈值电平降低到较低的相邻阈值电平导致仅仅一位数据的改变，从而提高了存储器系统的可靠性。 存储器系统还包括以多级单元模式或标准级单元模式存储阈值状态的能力。 在标准单元模式中，转换器电路直接传递二进制编码位，而不执行任何转换。

公开(公告)号：US5347484A

公开(公告)日：1994-09-13

申请号：US216766

申请日：1994-03-23

申请人： Phillip M. Kwong ,  Sachidanandan Sambandan ,  Sherif R. B. Sweha ,  Duane R. Mills

发明人： Phillip M. Kwong ,  Sachidanandan Sambandan ,  Sherif R. B. Sweha ,  Duane R. Mills

IPC分类号： G11C29/00 ,  G11C11/40

CPC分类号： G11C29/808

摘要： A nonvolatile memory device is described. The memory device includes a main memory array for storing data. The main memory array comprises a first block and a second block. A redundant memory array comprises a first redundant block and a second redundant block. The first redundant block comprises a first redundant column of memory cells and a second redundant column of memory cells. The second redundant block comprises a third redundant column of memory cells and a fourth redundant column of memory cells. A content addressable memory (CAM) comprises a first set of CAM cells for storing a first address of a first defective column in the main memory array and a second set of CAM cells for storing a second address of a second defective column in the main memory array. The first set of CAM cells cause the first redundant column in the first redundant block to replace the first defective column when the first defective column is in the first block. The first set of CAM cells cause the third redundant column in the second redundant block to replace the first defective column when the first defective column is in the second block. The second set of CAM cells cause the second redundant column in the first redundant block to replace the second defective column when the second defective column is in the first block. The second set of CAM cells cause the fourth redundant column in the second redundant block to replace the second defective column when the second defective column is in the second block.

摘要翻译： 描述非易失性存储器件。 存储器件包括用于存储数据的主存储器阵列。 主存储器阵列包括第一块和第二块。 冗余存储器阵列包括第一冗余块和第二冗余块。 第一冗余块包括存储器单元的第一冗余列和存储器单元的第二冗余列。 第二冗余块包括存储器单元的第三冗余列和存储器单元的第四冗余列。 内容可寻址存储器（CAM）包括用于存储主存储器阵列中的第一缺陷列的第一地址的第一组CAM单元和用于存储主存储器中的第二缺陷列的第二地址的第二组CAM单元 数组。 当第一个缺陷列在第一个块中时，第一组CAM单元使第一个冗余块中的第一个冗余列替换第一个缺陷列。 当第一个缺陷列在第二个块中时，第一组CAM单元使第二个冗余块中的第三个冗余列替换第一个缺陷列。 当第二个缺陷列在第一个块中时，第二组CAM单元使第一个冗余块中的第二个冗余列替换第二个缺陷列。 当第二个缺陷列在第二个块中时，第二组CAM单元使第二个冗余块中的第四个冗余列替换第二个缺陷列。