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    PROTOCOL FOR AUTHENTICATING FUNCTIONALITY IN A PERIPHERAL DEVICE
    1.
    发明申请
    PROTOCOL FOR AUTHENTICATING FUNCTIONALITY IN A PERIPHERAL DEVICE 有权
    用于在外围设备中识别功能的协议

    公开(公告)号：US20140032907A1

    公开(公告)日：2014-01-30

    申请号：US14051364

    申请日：2013-10-10

    申请人： NED M. SMITH ,  STEVEN E. WELLS ,  ROBERT W. STRONG

    发明人： NED M. SMITH ,  STEVEN E. WELLS ,  ROBERT W. STRONG

    IPC分类号： H04L9/32

    CPC分类号： H04L9/32 ,  G06F21/44 ,  G06F21/629 ,  G06F21/70 ,  G06F2221/2107 ,  H04L9/3252

    摘要： A protocol provides authentication of peripheral devices by a computing device to which the peripheral device connects. Computing devices include a verifier with a public key that authenticates multiple associated private keys. Private keys are embedded on peripheral devices. When the verifier is able to authenticate a connected peripheral, particular functionality is enabled that may not be enabled for peripherals that do not authenticate.

    摘要翻译： 协议通过外围设备连接的计算设备提供对外围设备的认证。 计算设备包括具有认证多个相关私钥的公开密钥的验证者。 私钥嵌入在外围设备上。 当验证者能够对连接的外围设备进行身份验证时，启用特定的功能，这些功能可能无法为不进行身份验证的外设启用。

    Duty cycle corrector for a random number generator
    2.
    发明授权
    Duty cycle corrector for a random number generator 失效
    随机数发生器的占空比校正器

    公开(公告)号：US06643374B1

    公开(公告)日：2003-11-04

    申请号：US09283096

    申请日：1999-03-31

    申请人： Steven E. Wells ,  David A. Ward

    发明人： Steven E. Wells ,  David A. Ward

    IPC分类号： H04L926

    CPC分类号： H04L9/0662 ,  H04L2209/12

    摘要： A method and apparatus for producing a corrected bit stream from a random bit stream output by a random bit source. Sequential pairs of bits in the random bit stream are compared. If both bits in a pair of bits are identical, the output bits are discarded. If both bits in a pair of bits are different, one bit of the pair of bits is taken as the output bit.

    摘要翻译： 一种用于由随机比特源输出的随机比特流产生校正比特流的方法和装置。 比较随机比特流中的比特序列。 如果一对位中的两个位相同，则输出位被丢弃。 如果一对比特中的两个比特不同，则将该比特中的一个比特作为输出比特。

    Method of managing defects in flash disk memories
    3.
    发明授权
    Method of managing defects in flash disk memories 失效
    管理闪存盘存储器缺陷的方法

    公开(公告)号：US6014755A

    公开(公告)日：2000-01-11

    申请号：US700676

    申请日：1996-08-12

    申请人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

    发明人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

    IPC分类号： G11C17/00 ,  G06F11/00 ,  G06F11/10 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/765 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/88 ,  G11C2029/0409

    摘要： A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

    摘要翻译： 一种用于监视闪存阵列的操作的方法，所述闪速存储器阵列被划分成单独的可擦除存储块，以便确保存储在阵列中的数据的完整性，其中每个读取或写入操作被验证以检测可能在操作中发生的错误 包括以下步骤：每当发生错误以进行错误发生以尝试至少一次重试操作以确定该错误是否可重复时，如果该错误被发现是可重复的，则应该从该块中删除指示有效数据的块，从该块中删除有效信息 如果发现错误是可重复的，并且从操作中移除具有可重复错误的块，则阻塞。

    Addressing modes for a dynamic single bit per cell to multiple bit per cell memory
    5.
    发明授权
    Addressing modes for a dynamic single bit per cell to multiple bit per cell memory 失效
    每个单元的动态单个位的寻址模式，每个单元存储器的多个位

    公开(公告)号：US5515317A

    公开(公告)日：1996-05-07

    申请号：US252920

    申请日：1994-06-02

    申请人： Steven E. Wells ,  Kurt B. Robinson

    发明人： Steven E. Wells ,  Kurt B. Robinson

    IPC分类号： G11C11/56 ,  G11C11/34

    CPC分类号： G11C11/5621 ,  G11C11/56 ,  G11C2211/5641 ,  G11C8/00

    摘要： A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode. The addressing scheme of the present invention maintains address coherency by exhibiting a n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, and by exhibiting a 1:1 correspondence between memory locations and the physical addresses when operating in the standard cell mode.

    摘要翻译： 存储器系统包含用于存储多个阈值电平的存储器单元，以表示“n”位数据的存储。 存储器系统包括用于生成多个物理地址的地址缓冲器，使得每个物理地址唯一地标识“j”个存储器单元的存储器位置。 为了寻址由单个物理地址标识的“n”位的一部分，地址缓冲器生成多级单元（MLC）地址。 存储器系统还包含用于允许选择多级单元（MLC）模式和标准单元模式的开关控制。 当存储器以标准单元模式运行时，选择电路允许每单元读取单个位，并且当存储器以多电平单元模式运行时，允许每个存储单元读取多个位数据。 本发明的寻址方案通过在以MLC模式操作时通过显示存储器位置和物理地址之间的1对应关系来维持地址一致性，并且当在标准中操作时通过显示存储器位置与物理地址之间的1：1对应关系 单元格模式。

    Method for assuring that an erase process for a memory array has been properly completed
    7.
    发明授权
    Method for assuring that an erase process for a memory array has been properly completed 失效
    确保存储器阵列的擦除处理已经被正确完成的方法

    公开(公告)号：US5369616A

    公开(公告)日：1994-11-29

    申请号：US207228

    申请日：1994-03-07

    申请人： Steven E. Wells ,  Eric J. Magnusson

    发明人： Steven E. Wells ,  Eric J. Magnusson

    IPC分类号： G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G06F13/16

    CPC分类号： G06F3/0601 ,  G11C16/102 ,  G11C16/16 ,  G06F2003/0694

    摘要： A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.

    摘要翻译： 一种用于确保在快闪EEPROM晶体管块上实施的擦除操作被可靠地执行的方法，包括以下步骤：每当闪存EEPROM阵列的块的擦除开始到阵列中的位置时写入，以指示 块的擦除已经开始，每当擦除快闪EEPROM阵列的块完成到阵列中的位置以指示块的擦除已经完成时，写入测试来确定阵列中的任何位置，表示该块 块的擦除已经开始，但是在向闪存EEPROM阵列施加电力时未完成，并且如果存在阵列中的任何位置，则重新启动擦除，这表示块的擦除已经开始但未完成。

    Method for writing to a flash memory array during erase suspend intervals
    8.
    发明授权
    Method for writing to a flash memory array during erase suspend intervals 失效
    在擦除暂停间隔期间写入闪存阵列的方法

    公开(公告)号：US5341330A

    公开(公告)日：1994-08-23

    申请号：US145732

    申请日：1993-11-01

    申请人： Steven E. Wells ,  Mark Winston ,  Virgil N. Kynett

    发明人： Steven E. Wells ,  Mark Winston ,  Virgil N. Kynett

    IPC分类号： G06F3/06 ,  G11C16/10 ,  G11C13/00

    CPC分类号： G06F3/0601 ,  G11C16/102 ,  G06F2003/0694 ,  G06F2212/2022

    摘要： A method for writing data to an entry in a portion of a flash EEPROM memory array during a period in which that portion of the array is being erased and writing is prohibited. The method includes writing the data to a new entry position apart from the portion of the array which is being erased along with a revision number which is greater than the revision number of the original data in the original portion of the array, writing of the busy condition of the original entry to a temporary storage position apart from the portion of the array which is being erased, and invalidating entries listed in the temporary storage position when the erase operation is concluded.

    摘要翻译： 在数据的该部分被擦除和写入的时段期间，将数据写入快闪EEPROM存储器阵列的一部分中的条目的方法被禁止。 该方法包括将数据写入除了正被擦除的阵列的部分之外的新的入口位置以及比阵列的原始部分中的原始数据的修订版本号大的修订版本号，写入忙 原始条目到除了被擦除的阵列的部分之外的临时存储位置的条件，以及当擦除操作结束时使临时存储位置中列出的条目无效。

    Secure hardware random number generator
    10.
    发明授权
    Secure hardware random number generator 有权
    安全硬件随机数发生器

    公开(公告)号：US07269614B2

    公开(公告)日：2007-09-11

    申请号：US10638097

    申请日：2003-08-07

    申请人： Steven E. Wells ,  V. Niles Kynett ,  Lance W. Dover

    发明人： Steven E. Wells ,  V. Niles Kynett ,  Lance W. Dover

    IPC分类号： G06F1/02

    CPC分类号： G06F7/588

    摘要： A random number generator comprises random number generation circuitry to generate and output random bits. The random number generator comprises interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits. The interface circuitry prevents outputting the same random bits more than once.

    摘要翻译： 随机数生成器包括产生和输出随机位的随机数生成电路。 随机数生成器包括用于接收和存储由随机数生成电路输出的随机位和输出随机位的接口电路。 接口电路防止多次输出相同的随机位。