公开(公告)号：US10328469B1

公开(公告)日：2019-06-25

申请号：US15667607

申请日：2017-08-02

申请人： Binod Shah ,  Prasanna Shah

发明人： Binod Shah ,  Prasanna Shah

IPC分类号： B09B3/00 ,  A61J7/00 ,  B65F1/00

摘要： A pill management device includes a portable reservoir having a pill-receiving inlet and an access door spaced from the pill-receiving inlet, a pill-crushing mechanism disposed within the reservoir and configured to transform a solid pill, introduced via the pill-receiving inlet, to pill powder, and a locking mechanism in communication with the access door and the pill-receiving inlet for preventing unauthorized access to the pill powder housed within the reservoir. Advantageously, the locking mechanism locks the access door and the pill-receiving inlet.

公开(公告)号：US20060090014A1

公开(公告)日：2006-04-27

申请号：US10975132

申请日：2004-10-27

申请人： Kar Wong ,  Mikal Hunsaker ,  Prasanna Shah

发明人： Kar Wong ,  Mikal Hunsaker ,  Prasanna Shah

IPC分类号： G06F3/00

CPC分类号： G06F13/423

摘要： Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.

摘要翻译： 外围组件互连（PCI）Express的事务层链接处理。 初始化I / O控制器的输入/输出（I / O）控制器端口和设备的设备端口之间的链接，其中链路包括物理层，数据链路层和事务层。 在没有软件干预的情况下，在数据链路关闭状态之后，事务层被恢复。

公开(公告)号：US20060088046A1

公开(公告)日：2006-04-27

申请号：US10974573

申请日：2004-10-26

申请人： Kar Wong ,  Mikal Hunsaker ,  Prasanna Shah

发明人： Kar Wong ,  Mikal Hunsaker ,  Prasanna Shah

IPC分类号： H04L12/56

CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9057

摘要： Queue resource sharing for an input/output controller. A shared resource queue is associated with a plurality of ports. The shared resource queue includes a plurality of sections allocated for use by at least one of the plurality of ports based at least in part on a port bandwidth configuration of the plurality of ports.

摘要翻译： 用于输入/输出控制器的队列资源共享。 共享资源队列与多个端口相关联。 至少部分地基于多个端口的端口带宽配置，共享资源队列包括被分配用于由多个端口中的至少一个端口使用的多个部分。

公开(公告)号：US5555510A

公开(公告)日：1996-09-10

申请号：US284185

申请日：1994-08-02

申请人： Jerry Verseput ,  Fong-Shek Lam ,  Prasanna Shah

发明人： Jerry Verseput ,  Fong-Shek Lam ,  Prasanna Shah

IPC分类号： G06F11/20 ,  G06F13/40 ,  H02H9/00

CPC分类号： H02H9/004 ,  G06F13/4072 ,  Y10T307/461

摘要： A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state. Next, detect that the PC card has been completely inserted or removed by monitoring the ground pins or the card detect signal pins. Next, apply power to the PCMCIA card socket. After a delay return the common address, data and control lines to their normal operating impedance level.

摘要翻译： 一种适用于具有连接到CPU的系统总线的主机系统的方法和具有状态寄存器的PCMCIA控制器，用于向CPU发送信号的装置和能够处于正常和高阻抗状态的行缓冲器的装置。 多针连接器位于每个卡插槽中，并连接到线路缓冲器。 每个连接器具有公共地址，数据和控制引脚，电源引脚，接地引脚长于数据引脚，并且卡检测信号引脚短于信号引脚。 第一步是通过监测地面和卡检测信号引脚来检测PCMCIA卡插入或取出插座的开始。 检测后，通过断言退出信号，开始终止公共地址，数据和控制线的所有CPU使用。 接下来，通过监视控制器中的状态寄存器来确定是否终止使用。 接下来，将公共地址，数据和控制线置于高阻态。 接下来，通过监视接地引脚或卡检测信号引脚来检测PC卡是否完全插入或取出。 接下来，为PCMCIA卡插座供电。 经过延时后，公共地址，数据和控制线路恢复正常的工作阻抗级别。