公开(公告)号：US20110168554A1

公开(公告)日：2011-07-14

申请号：US13070767

申请日：2011-03-24

申请人： QI HAU ZHANG ,  Ming Li ,  Chorng Shry Niou ,  Scott Liao

发明人： QI HAU ZHANG ,  Ming Li ,  Chorng Shry Niou ,  Scott Liao

IPC分类号： C23C14/34

CPC分类号： G01N23/2276 ,  H01L22/12

摘要： An apparatus for treatment of a sample for the manufacture of integrated circuits includes a holder apparatus and a stage which is coupled to the holder apparatus. The stage is capable of holding a portion of a sample to be analyzed. The apparatus also includes a shield that is operably coupled to the stage to block a portion of the sample. The shield is capable of movement relative to the sample to block one or more portions of the sample. The shield is provided on a track member and is movable from a first spatial location to a second spatial location on the track member. The apparatus further includes an enclosure surrounding an entirety of the sample and the shield.

摘要翻译： 用于处理用于制造集成电路的样品的装置包括保持装置和与保持装置连接的台。 该阶段能够容纳要分析的样品的一部分。 该装置还包括可操作地耦合到载物台以阻挡样品的一部分的屏蔽件。 屏蔽能够相对于样品移动以阻挡样品的一个或多个部分。 屏蔽件设置在轨道构件上并且可从轨道构件上的第一空间位置移动到第二空间位置。 该装置还包括围绕整个样品和屏蔽件的外壳。

公开(公告)号：US07504269B2

公开(公告)日：2009-03-17

申请号：US11378400

申请日：2006-03-16

申请人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

发明人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

IPC分类号： G01R31/26

CPC分类号： G01N23/2276 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

摘要翻译： 用于分析用于制造集成电路的样品的方法，例如， MOS晶体管，专用集成电路，存储器件，微处理器，片上系统。 该方法包括提供集成电路芯片，其具有至少一个感兴趣区域的表面区域，例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层，而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

公开(公告)号：US07927893B2

公开(公告)日：2011-04-19

申请号：US12364977

申请日：2009-02-03

申请人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

发明人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

IPC分类号： H01L21/66

CPC分类号： G01N23/2276 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

摘要翻译： 用于分析用于制造集成电路的样品的方法，例如， MOS晶体管，专用集成电路，存储器件，微处理器，片上系统。 该方法包括提供集成电路芯片，其具有至少一个感兴趣区域的表面区域，例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层，而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

公开(公告)号：US20090305440A1

公开(公告)日：2009-12-10

申请号：US12364977

申请日：2009-02-03

申请人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

发明人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

IPC分类号： H01L21/66 ,  C23C14/34

CPC分类号： G01N23/2276 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

摘要翻译： 用于分析用于制造集成电路的样品的方法，例如， MOS晶体管，专用集成电路，存储器件，微处理器，片上系统。 该方法包括提供集成电路芯片，其具有至少一个感兴趣区域的表面区域，例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层，而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。