公开(公告)号：US20040194047A1

公开(公告)日：2004-09-30

申请号：US10668089

申请日：2003-09-23

Applicant: RENESAS TECHNOLOGY CORP ,  RENESAS LSI DESIGN CORPORATION

Inventor： Shino Matsubara

IPC: G06F009/45 ,  G06F017/50 ,  G06F009/455

CPC classification number: G06F17/5077 ,  G06F17/5072

Abstract: A layout design apparatus can develop a semiconductor integrated circuit in a shorter period at a lower cost. It includes an initial layout section for performing placement and routing using a netlist of the entire semiconductor integrated circuit such that a first circuit layout whose wiring consists of n (nnull2) wiring layers is formed in a first circuit region, and a second circuit layout, which has wiring consisting of (nnullm) (m

Abstract translation: 布局设计装置可以以更低的成本在更短的时间内开发半导体集成电路。 它包括用于使用整个半导体集成电路的网表执行放置和布线的初始布局部分，使得其布线由n（n> = 2）布线层构成的第一电路布局形成在第一电路区域中，并且第二电路布局 具有由（nm）（m

公开(公告)号：US20040128523A1

公开(公告)日：2004-07-01

申请号：US10615792

申请日：2003-07-10

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS LSI DESIGN CORPORATION

Inventor： Shuzo Fujioka

IPC: H04L009/32 ,  G06F011/30

CPC classification number: G06F21/72 ,  G06F2221/2129

Abstract: An information security microcomputer includes an encryption circuit encrypting and decrypting information, an authentication program authenticating an ICE main body, and a CPU performing entire control of the information security microcomputer. CPU stops at least a part of a function of the information security microcomputer when the ICE main body cannot be authenticated. Therefore, an unauthorized person cannot use the information security microcomputer as an ICE microcomputer so that security can be improved.

Abstract translation: 信息安全微计算机包括加密和解密信息的加密电路，认证ICE主体的认证程序和执行信息安全微计算机的整个控制的CPU。 当ICE主体无法认证时，CPU至少停止信息安全微计算机的一部分功能。 因此，未授权的人不能使用信息安全微计算机作为ICE微型计算机，以提高安全性。

公开(公告)号：US20040164988A1

公开(公告)日：2004-08-26

申请号：US10669261

申请日：2003-09-25

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS LSI DESIGN CORPORATION.

Inventor： Seiji Matsumoto

IPC: G06F013/00

CPC classification number: G09G5/003 ,  G09G2340/12

Abstract: An on-screen display unit includes OSD (on-screen display) RAMs each for storing data on one of OSD blocks to be subjected to OSD; a memory bus for transferring data to be stored to the OSD RAMs from a CPU; and an OSD local bus for transferring the data stored in the OSD RAMs to make the OSD. The OSD RAMs are supplied with the data to be stored through the control of switches alternately, and transfer the stored data to the OSD local bus 12 alternately. The on-screen display unit can cope with a high frequency OSD clock signal, and carry out the OSD normally.

Abstract translation: 屏幕显示单元包括OSD（屏幕显示）RAM，每个RAM用于存储要进行OSD的OSD块之一的数据; 用于从CPU传送要存储到OSD RAM的数据的存储器总线; 以及用于传送存储在OSD RAM中的数据以进行OSD的OSD本地总线。 交替地通过开关控制的OSD RAM来提供要存储的数据，并将存储的数据交替地传送到OSD本地总线12。 屏幕显示单元可以处理高频OSD时钟信号，并正常执行OSD。

公开(公告)号：US20040264233A1

公开(公告)日：2004-12-30

申请号：US10874360

申请日：2004-06-24

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS LSI DESIGN CORPORATION

Inventor： Kazuhiko Fukushima ,  Atsuo Yamaguchi

IPC: G11C011/22

CPC classification number: G06F7/588 ,  G11C29/36 ,  G11C2029/3602

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract translation: 随机数发生器包括具有异或门的环形振荡器和四个反相器一起形成环路。 该回路进入具有低电平的起始信号的稳定状态，并振荡具有高电平的起始信号。 当启动信号具有比循环的延迟时间短的宽度的脉冲时，响应地输出节点，顺序地进入在高电平和低电平之间的亚稳态盘旋。 亚稳态波形随时间变小，最终消失。 由于亚稳态在长寿中不能被控制，所以随机数节点消失。 因此，计数器根据亚稳态的寿命输出用作真随机数数据的信号。 因此可以实现小型化并且具有降低的功率消耗和高性能的随机数发生器。

公开(公告)号：US20040257124A1

公开(公告)日：2004-12-23

申请号：US10873309

申请日：2004-06-23

Applicant: RENESAS TECHNOLOGY CORP. ,  RENESAS LSI DESIGN CORPORATION

Inventor： Masahiro Araki ,  Chieko Hayashi

IPC: H03C003/00

CPC classification number: H03L7/0812 ,  H03L7/081 ,  H03L7/0996 ,  H03L7/23 ,  H03L7/235

Abstract: In a spread spectrum clock generator, a DLL circuit delays an oscillation clock signal from a VCO and outputs ten delay clock signals having different phases respectively. A selector selects any one of the ten delay clock signals, and outputs a selected clock signal. A control circuit controls a signal selection operation of the selector. A feedback frequency divider divides a frequency of the selected clock signal by a frequency division ratio N, and generates a comparison clock signal. In this manner, a phase of the comparison clock signal can be fine-tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be obtained.

Abstract translation: 在扩频时钟发生器中，DLL电路延迟来自VCO的振荡时钟信号，并分别输出具有不同相位的十个延迟时钟信号。 选择器选择十个延迟时钟信号中的任何一个，并输出所选择的时钟信号。 控制电路控制选择器的信号选择操作。 反馈分频器将所选择的时钟信号的频率除以分频比N，并产生比较时钟信号。 以这种方式，可以微调比较时钟信号的相位。 因此，可以获得能够高精度进行频率调制的扩频时钟发生器。

公开(公告)号：US20040066272A1

公开(公告)日：2004-04-08

申请号：US10603663

申请日：2003-06-26

Applicant: RENESAS TECHNOLOGY CORPORATION ,  RENESAS LSI DESIGN CORPORATION

Inventor： Katsumi Kitagaki ,  Takashi Hirosawa ,  Harufusa Kondoh ,  Kiyoshi Nakakimura

IPC: G05B023/02

CPC classification number: H04L61/2038 ,  H04L29/12254

Abstract: A house code assigning device includes a communication unit for sending a command for requesting transmission of a house code to electronic equipment included in a system and for receiving a house code from the electronic equipment, a verification unit for verifying whether or not a house code received by the communication unit is correct and for outputting a verification result showing whether or not the house code received by the communication unit is correct, and a display control unit for controlling a light emitting unit according to the verification result from the verification unit.

Abstract translation: 房屋代码分配装置包括：通信单元，用于发送用于请求发送房屋代码的命令到包括在系统中的电子设备并用于从电子设备接收房屋代码的通信单元;验证单元，用于验证是否接收到房屋代码 通信单元是正确的，并且用于输出表示由通信单元接收的房屋代码是否正确的验证结果;以及显示控制单元，用于根据验证单元的验证结果来控制发光单元。