公开(公告)号：US20100115207A1

公开(公告)日：2010-05-06

申请号：US12262514

申请日：2008-10-31

Applicant: Rajan ARORA ,  Randy BISHOP ,  Arnold GINETTI ,  Gilles S.C. LAMANT

Inventor： Rajan ARORA ,  Randy BISHOP ,  Arnold GINETTI ,  Gilles S.C. LAMANT

IPC: G06F12/08

CPC classification number: G06F17/3048

Abstract: An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Abstract translation: 公开了一种改进的pcell缓存方法，其实现了对pcell高速缓存的安全和有效的多用户访问。 锁定结构与计数器结合使用，为pcell高速缓存提供多用户支持。 当缓存的pcell数据发生修改时，更新到适当的计数器）。 检查计数器的值以确定实体操作的数据项是否仍然有效，或者另一个并发实体是否对数据进行了更改。

公开(公告)号：US20080232219A1

公开(公告)日：2008-09-25

申请号：US12075982

申请日：2008-03-14

Applicant: Yugal K. Sharma ,  Tad Richman ,  Kurt Beyer ,  Rajan Arora

Inventor： Yugal K. Sharma ,  Tad Richman ,  Kurt Beyer ,  Rajan Arora

IPC: G11B7/28

CPC classification number: G11B7/28 ,  G06K9/00973

Abstract: A system and method for creating digital content from a plurality of legacy media formats, such as paper, CD, VHS, DVD, etc. A coordination node is utilized to balance the computation load between the various processing units, particularly those involved in the second stage of operation. Extraction units are used to input various types of information into the system as digital media. Once the information has been extracted, the coordination node and its associated software determine the load on each processing unit in the second stage and based on this and other factors, determine which processing unit will perform the conversion. The output is then stored in storage devices. This approach maximizes system utilization, while being more cost efficient than traditional extraction systems.

Abstract translation: 用于从诸如纸，CD，VHS，DVD等的多种传统媒体格式创建数字内容的系统和方法。协调节点用于平衡各种处理单元之间的计算负荷，特别是涉及第二 操作阶段 提取单元用于将各种类型的信息输入到系统中作为数字媒体。 一旦提取了信息，协调节点及其相关联的软件确定第二阶段中每个处理单元的负载，并且基于这个和其他因素，确定哪个处理单元将执行转换。 然后将输出存储在存储设备中。 这种方法使系统利用率最大化，同时比传统的提取系统更具成本效益。

公开(公告)号：US07506277B1

公开(公告)日：2009-03-17

申请号：US11485039

申请日：2006-07-11

Applicant: Rajan Arora ,  Umesh Sisodia ,  Anurag Jain

Inventor： Rajan Arora ,  Umesh Sisodia ,  Anurag Jain

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5081 ,  G06F2217/64

Abstract: An improved method, system, computer program product, and electronic design structures which provides the flexibility to IC designers to be able to relax the design rules to increase the yield and improve the layout productivity is disclosed. In some disclosed approaches, automated interactive aids and batch tools are provided which can assist in optimizing the final layouts for yield at the initial placement and/or routing stages for optimizing yield. Provided in some disclosed approaches are automated capability to layout designers at the mos devices level to configure mos devices as per different DFY recommendations from the foundry without negative effects on the overall chip area (or cell size). The design rules may be relaxed selectively on an instance basis and wherever possible or desirable.

Abstract translation: 公开了一种改进的方法，系统，计算机程序产品和电子设计结构，其提供了IC设计者能够放松设计规则以提高产量并提高布局生产率的灵活性。 在一些公开的方法中，提供了自动交互式辅助工具和批量工具，其可以帮助优化用于优化产量的初始放置和/或路由阶段的产量的最终布局。 在一些公开的方法中提供了在mos器件级布局设计者的自动化能力，以根据来自铸造厂的不同DFY建议配置mos器件，而不对整个芯片面积（或单元大小）产生负面影响。 设计规则可以在实例基础上并且在可能或期望的情况下选择性地放松。

公开(公告)号：US08364656B2

公开(公告)日：2013-01-29

申请号：US12262514

申请日：2008-10-31

Applicant: Rajan Arora ,  Randy Bishop ,  Arnold Ginetti ,  Gilles S. C. Lamant

Inventor： Rajan Arora ,  Randy Bishop ,  Arnold Ginetti ,  Gilles S. C. Lamant

IPC: G06F12/08

CPC classification number: G06F17/3048

Abstract: An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counter(s). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Abstract translation: 公开了一种改进的pcell缓存方法，其实现了对pcell高速缓存的安全和有效的多用户访问。 锁定结构与计数器结合使用，为pcell高速缓存提供多用户支持。 当缓存的pcell数据发生修改时，更新到相应的计数器。 检查计数器的值以确定实体操作的数据项是否仍然有效，或者另一个并发实体是否对数据进行了更改。

公开(公告)号：US20100205575A1

公开(公告)日：2010-08-12

申请号：US12489265

申请日：2009-06-22

Applicant: Rajan Arora ,  Chayan Majumder ,  Sandipan Ghosh ,  Anil Kumar Arya

Inventor： Rajan Arora ,  Chayan Majumder ,  Sandipan Ghosh ,  Anil Kumar Arya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F3/04812

Abstract: Disclosed are methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments disclosed herein provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments disclosed herein are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.

Abstract translation: 公开了用于编辑电路的方法，系统，计算机程序产品，其促进和加速电路布局。 本文公开的实施例向用户提供高空编辑能力，使用户能够更容易地选择拥挤布局和示意图中的电路项目，并且在拥挤的布局和原理图中相对于彼此修改和布置电路项目。 本文公开的另外的实施例旨在使得EDA命令等能够具有上下文敏感性，邻域感知和/或预测用户意图的能力。

公开(公告)号：US08490038B1

公开(公告)日：2013-07-16

申请号：US13595942

申请日：2012-08-27

Applicant: Rajan Arora ,  Arnold Jean-Marie Gustave Ginetti ,  Gautam Kumar

Inventor： Rajan Arora ,  Arnold Jean-Marie Gustave Ginetti ,  Gautam Kumar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: A system, method, and computer program product for automatically placing contact cuts in integrated circuit layouts, particularly in guard rings, inter-layer via connections, and various space-filling structures typically defined by polygons or paths. Areas to be filled with contact cuts are partitioned horizontally and vertically, and decomposed into shared and exclusive type regions that are sorted directionally. Contact cuts are placed in each region according to its type and according to relevant design rules on contact cut spacing and enclosure constraints. Contact cuts that may cause design rule violations are deleted. Narrow jogs or cuts, merged shared regions, and non-orthogonal edges or segments in the decomposed regions are handled by alternate embodiments. The result is automated contact cut placement, even for merged/chopped layout features, that is generally more symmetric, collinear, and adds an optimal number of contact cuts in most cases than with existing tools.

Abstract translation: 一种系统，方法和计算机程序产品，用于在集成电路布局中自动放置接触切割，特别是在保护环，层间通孔连接以及通常由多边形或路径定义的各种空间填充结构中。 填充有接触切割的区域水平和垂直分割，并分解为定向分类的共享和排他型区域。 接触切割根据其类型和根据接触切割间距和外壳约束的相关设计规则放置在每个区域中。 可能导致设计规则违规的联系人削减被删除。 通过替代实施例来处理分解区域中的窄步进或切割，合并的共享区域和非正交边缘或段。 结果是自动接触切割放置，即使是合并/切碎的布局特征，通常更为对称，共线，并且在大多数情况下与现有工具相比，增加了最佳数量的接触切割。

公开(公告)号：US08612923B2

公开(公告)日：2013-12-17

申请号：US12489265

申请日：2009-06-22

Applicant: Rajan Arora ,  Chayan Majumder ,  Sandipan Ghosh ,  Anil Kumar Arya

Inventor： Rajan Arora ,  Chayan Majumder ,  Sandipan Ghosh ,  Anil Kumar Arya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F3/04812

Abstract: Methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.

Abstract translation: 用于编辑电路的方法，系统，计算机程序产品，促进和加速电路布局。 实施例向用户提供高空编辑能力，使得用户能够更容易地选择拥挤的布局和原理图中的电路项目，并且在拥挤的布局和示意图中修改和布置彼此的电路项目。 另外的实施例旨在使得EDA命令等能够具有上下文敏感性，邻域感知和/或预测用户意图的能力。

公开(公告)号：US08271909B2

公开(公告)日：2012-09-18

申请号：US12366911

申请日：2009-02-06

Applicant: Chayan Majumder ,  Sandipan Ghosh ,  Anil Kumar Arya ,  Pawan Kumar Fangaria ,  Rajan Arora

Inventor： Chayan Majumder ,  Sandipan Ghosh ,  Anil Kumar Arya ,  Pawan Kumar Fangaria ,  Rajan Arora

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Embodiments of the invention provide system and methods for EDA tools. Specifically, some embodiments of the invention provide an input infrastructure for EDA tools that gathers pertinent information surrounding an input cursor's present locality (or neighborhood) and then analyzes the pertinent information in view of an issued command to automatically determine suitable targets or subsequent operations that a user of the EDA tool may want to select next.

Abstract translation: 本发明的实施例提供了EDA工具的系统和方法。 具体来说，本发明的一些实施例为EDA工具提供输入基础设施，其收集围绕输入光标的当前位置（或邻域）的相关信息，然后根据发出的命令来分析相关信息以自动确定合适的目标或后续操作 EDA工具的用户可能想要选择下一个。

公开(公告)号：US07949987B1

公开(公告)日：2011-05-24

申请号：US12028546

申请日：2008-02-08

Applicant: Arnold Ginetti ,  Gilles S. C. Lamant ,  Randy Bishop ,  Rajan Arora

Inventor： Arnold Ginetti ,  Gilles S. C. Lamant ,  Randy Bishop ,  Rajan Arora

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: An improved method and system are disclosed for utilizing abstracted versions of layout portions in conjunction with parameterized cells (pcells). One significant advantage is that abstracted versions of pcells can be generated from normal pcells and stored in a pcell cache, which avoids the need to abstract layout pcells on the fly.

Abstract translation: 公开了一种改进的方法和系统，用于结合参数化单元（pcell）来利用布局部分的抽象版本。 一个重要的优点是pcell的抽象版本可以从正常的pcell生成并存储在pcell缓存中，这避免了在飞行中抽象布局pcell。