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公开(公告)号：US09306596B2
公开(公告)日：2016-04-05
申请号：US14317698
申请日：2014-06-27
CPC分类号： G06F12/0646 , G06F2212/1021 , G06F2212/401 , G11C15/00 , G11C15/04 , H03M7/3059 , H03M7/3084 , H03M7/3086 , H03M7/40
摘要： Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits.
摘要翻译： 公开了一种集成电路，其包括包括第一部分和第二部分的存储器件。 第一部分是具有第一组单元的第一类型的内容可寻址存储器（CAM），并且第二部分是具有第二组单元格的第二类型的CAM。 第一组单元格小于第二组单元格。 集成电路还包括耦合到存储器件的解压加速器，解压加速器以产生多个长度代码。 多个长度码中的每一个包括至少一个位。 使用从包括多个符号的编码数据流接收的符号来生成多个长度码。 所述解压缩加速器进一步按照它们各自的位数按顺序将所述多个长度代码存储在所述存储器件的第一部分中。
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2.发明申请ARCHITECTURE AND METHOD FOR HYBRID CIRCUIT-SWITCHED AND PACKET-SWITCHED ROUTER 有权用于混合电路切换和分组交换路由器的架构和方法公开(公告)号：US20150071282A1
公开(公告)日：2015-03-12
申请号：US14129544
申请日：2013-09-06
IPC分类号： H04L12/64
CPC分类号： H04L12/6418 , G06F15/7825 , H04L49/109 , H04L49/251 , H04L49/252 , H04L49/9042
摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.
摘要翻译： 用于执行电路交换路由和分组交换路由以用于网络通信的技术和机制。 在一个实施例中，路由器评估由路由器接收的分组的控制信息，评估以检测分组是否包括用于边带通信的数据。 基于该评估，路由器从路由器的多个模式中进行选择，该多个模式包括在网络中路由用于边带数据的分组交换通信的分组的第一模式。 多个模式还包括根据分组配置电路交换信道的第二模式。 在另一个实施例中，路由器确定用于在分层网络中路由分组的方向，其中所述方向的确定基于所述分级网络的层级中的路由器的级别。
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3.发明申请公开(公告)号：US20140229741A1
公开(公告)日：2014-08-14
申请号：US13993545
申请日：2011-12-30
CPC分类号： G06F21/72 , G06F21/60 , H04L9/0631 , H04L2209/122
摘要： A different set of polynomials may be selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.
摘要翻译： 可以为加密和解密加速器选择不同的多项式集合。 也就是说，不同的多项式组用于加密和解密，每组被选择为使用较少的区域并为存储器加密引擎提供更多的功率。 这在一些实施例中是有利的，因为存储器读取操作通常比存储器写入更为关键和延迟敏感。
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公开(公告)号：US20130271199A1
公开(公告)日：2013-10-17
申请号：US13997584
申请日：2011-11-14
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K3/356182 , H03K19/018507
摘要： Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption.
摘要翻译： 通过中压控制争用中断实现电压电平转换的方法和系统。 电压电平移位器（VLS）可以包括电压电平移位电路，用于将输入逻辑状态从输入电压摆幅电平移位到输出电压摆幅。 VLS可以包括争用电路，争用中断器和中断控制器，以产生具有临时电压摆幅的争用中断控制。 临时电压摆幅的下限可以对应于输出电压摆幅的下限。 临时电压摆幅的上限可以对应于输入电压摆幅的上限。 可以实现VLS以实现水平移位真实和互补的逻辑状态，例如用共源共栅电压开关逻辑（CVSL）。 临时电压控制的争用中断器可能有助于在相对较小的延迟和相对较小的功率和面积消耗的情况下，在竞争中断器的基于过程的电压可靠限度内维持电压。
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公开(公告)号：US20100082718A1
公开(公告)日：2010-04-01
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F7/00
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译： 描述了PopCount和BitScan的合并数据路径。 硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。 选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。 如果选择了BitScan操作，则输入字被编码。 压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。 压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。
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公开(公告)号：US07592835B2
公开(公告)日：2009-09-22
申请号：US11966307
申请日：2007-12-28
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically reconfigurable to perform a plurality of logical functions.
摘要翻译： 提供了包括可配置逻辑块（CLB）阵列的协处理器系统。 每个CLB包括多个查找表和多个加法器。 每个CLB可以是动态可重构的以执行多个逻辑功能。
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公开(公告)号：US07325024B2
公开(公告)日：2008-01-29
申请号：US10728127
申请日：2003-12-04
IPC分类号： G06F7/50
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译： 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。
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8.发明授权公开(公告)号：US07209395B2
公开(公告)日：2007-04-24
申请号：US10953202
申请日：2004-09-28
CPC分类号： G11C11/413 , G11C2207/007
摘要： A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.
摘要翻译： 一种设备包括多个存储单元。 每个存储单元包括耦合到位线的晶体管堆叠。 访问模式期间位线上的电荷值表示存储在访问存储单元中的数据的值。 在非访问模式期间，晶体管堆叠的所有晶体管都被关闭以节省功率。 无论存储在存储器单元中的数据的值如何，晶体管都截止。
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公开(公告)号：US07188134B2
公开(公告)日：2007-03-06
申请号：US09967240
申请日：2001-09-28
IPC分类号： G06F7/50
摘要： An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.
摘要翻译： 一种加法器，用于对处理器的算术逻辑单元中的两个二进制数进行求和。 加法器包括适于生成第一预定数量的进位的稀疏进位合并电路和耦合到稀疏进位合并电路并适于产生第二预定数量进位信号的多个中间进位发生器。 加法器还包括耦合到中间进位发生器和稀疏进位合并电路的多个条件和发生器，以提供两个二进制数的和。 加法器还可以包括多路复用器恢复电路，其实现加法器核的单轨动态实现。
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公开(公告)号：US06614680B2
公开(公告)日：2003-09-02
申请号：US10172277
申请日：2002-06-13
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
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