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    USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION
    2.
    发明申请
    USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION 有权
    使用深色位置减少物理不可靠功能（PUF）错误率，而不会存储明显的位置

    公开(公告)号：US20150178143A1

    公开(公告)日：2015-06-25

    申请号：US14140243

    申请日：2013-12-24

    申请人： Sanu K. Mathew ,  Sudhir K. Satpathy ,  Patrick Koeberl ,  Jiangtao Li ,  Ram K. Krishnamurthy ,  Anand Rajan

    发明人： Sanu K. Mathew ,  Sudhir K. Satpathy ,  Patrick Koeberl ,  Jiangtao Li ,  Ram K. Krishnamurthy ,  Anand Rajan

    IPC分类号： G06F11/07

    CPC分类号： G06F11/0793 ,  G06F7/00 ,  G06F7/588 ,  G06F11/0745 ,  G11C7/24 ,  H04L9/3278 ,  H04L9/34

    摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.

    摘要翻译： 描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。 计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。 安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。 暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。 暗位表示PUF组件的PUF值在暗位窗口期间不稳定。 当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为 黑暗的一点

    APPARATUS AND METHOD FOR SKEIN HASHING
    5.
    发明申请
    APPARATUS AND METHOD FOR SKEIN HASHING 有权
    装置和方法进行滑雪

    公开(公告)号：US20150023500A1

    公开(公告)日：2015-01-22

    申请号：US14507427

    申请日：2014-10-06

    申请人： Farhana Sheikh ,  Jesse Walker ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

    发明人： Farhana Sheikh ,  Jesse Walker ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

    IPC分类号： H04L9/08

    CPC分类号： H04L9/0861 ,  H04L9/0618 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/0816 ,  H04L2209/125 ,  H04L2209/24 ,  H04N1/32277

    摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.

    摘要翻译： 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。

    Variable virtual ground domino logic with leakage control
    6.
    发明授权
    Variable virtual ground domino logic with leakage control 有权
    具有泄漏控制的可变虚拟地面多米诺逻辑

    公开(公告)号：US06404234B1

    公开(公告)日：2002-06-11

    申请号：US09851917

    申请日：2001-05-09

    申请人： Steven K. Hsu ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

    发明人： Steven K. Hsu ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.

    摘要翻译： 多米诺逻辑电路和方法包括至少两个串联连接的多米诺逻辑级，每个多米诺逻辑级包括动态级和静态级。 当接收到的时钟信号和第二多米诺逻辑级的动态输出均为高电平时，第一多米诺逻辑逻辑静态级的可变虚拟接地切换到低于电路接地电平的电压电平，表明第二多米诺逻辑电路级处于评估状态 相。

    HARDWARE-EMBEDDED KEY BASED ON RANDOM VARIATIONS OF A STRESS-HARDENED INEGRATED CIRCUIT
    7.
    发明申请
    HARDWARE-EMBEDDED KEY BASED ON RANDOM VARIATIONS OF A STRESS-HARDENED INEGRATED CIRCUIT 有权
    基于应力硬化电路的随机变化的硬件嵌入式键

    公开(公告)号：US20140266297A1

    公开(公告)日：2014-09-18

    申请号：US13889849

    申请日：2013-05-08

    申请人： Sanu K. Mathew ,  Rachael J. Parker ,  Ram K. Krishnamurthy

    发明人： Sanu K. Mathew ,  Rachael J. Parker ,  Ram K. Krishnamurthy

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00369 ,  H03K19/00315

    摘要： An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.

    摘要翻译： 被设计成用于断言多个可能的输出状态之一（每个具有相等的概率）的IC单元被实现为基于IC单元内的随机变化来断言多个输出状态中的预定的一个，例如随机过程变化。 IC单元阵列可配置为在上电时提供硬件嵌入式密钥，该特征是选择的IC单元的随机变化的组合，在制造之前和之后都能够防止篡改，并且能够耐老化，瞬时热噪声， 和环境变化，如电压和温度波动。 该密钥可以用作但不限于平台根密钥，高带宽数字内容保护（HDCP）密钥，增强型隐私标识（EPID）密钥和/或高级访问内​​容系统（AACS）密钥）。 还公开了基于IC电池的输出状态来测量IC电池的稳定性和应力硬化的技术。

    Combined set bit count and detector logic
    8.
    发明授权
    Combined set bit count and detector logic 有权
    组合位计数和检测器逻辑

    公开(公告)号：US08214414B2

    公开(公告)日：2012-07-03

    申请号：US12242727

    申请日：2008-09-30

    申请人： Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Shay Gueron ,  Vasantha K. Erraguntla

    发明人： Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Shay Gueron ,  Vasantha K. Erraguntla

    IPC分类号： G06F15/00

    CPC分类号： G06F7/74 ,  G06F7/607

    摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).

    摘要翻译： 描述了PopCount和BitScan的合并数据路径。 硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。 选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。 如果选择了BitScan操作，则输入字被编码。 压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。 压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

    Split path multiply accumulate unit
    10.
    发明授权
    Split path multiply accumulate unit 有权
    分路径乘积累积单位

    公开(公告)号：US08577948B2

    公开(公告)日：2013-11-05

    申请号：US12886012

    申请日：2010-09-20

    申请人： Suresh Srinivasan ,  Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Vasantha K. Erraguntla

    发明人： Suresh Srinivasan ,  Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Vasantha K. Erraguntla

    IPC分类号： G06F7/483

    CPC分类号： G06F9/3893 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036

    摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及 如果差值大于阈值，则处理指令执行的第二路径。 基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。 描述和要求保护其他实施例。