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    COMBINED SET BIT COUNT AND DETECTOR LOGIC
    1.
    发明申请
    COMBINED SET BIT COUNT AND DETECTOR LOGIC 有权
    组合设置位计数和检测器逻辑

    公开(公告)号：US20100082718A1

    公开(公告)日：2010-04-01

    申请号：US12242727

    申请日：2008-09-30

    申请人： Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Shay Gueron ,  Vasantha K. Erraguntla

    发明人： Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Shay Gueron ,  Vasantha K. Erraguntla

    IPC分类号： G06F7/00

    CPC分类号： G06F7/74 ,  G06F7/607

    摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).

    摘要翻译： 描述了PopCount和BitScan的合并数据路径。 硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。 选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。 如果选择了BitScan操作，则输入字被编码。 压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。 压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

    Combined set bit count and detector logic
    2.
    发明授权
    Combined set bit count and detector logic 有权
    组合位计数和检测器逻辑

    公开(公告)号：US08214414B2

    公开(公告)日：2012-07-03

    申请号：US12242727

    申请日：2008-09-30

    申请人： Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Shay Gueron ,  Vasantha K. Erraguntla

    发明人： Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Shay Gueron ,  Vasantha K. Erraguntla

    IPC分类号： G06F15/00

    CPC分类号： G06F7/74 ,  G06F7/607

    摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).

    摘要翻译： 描述了PopCount和BitScan的合并数据路径。 硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。 选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。 如果选择了BitScan操作，则输入字被编码。 压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。 压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

    Split path multiply accumulate unit
    3.
    发明授权
    Split path multiply accumulate unit 有权
    分路径乘积累积单位

    公开(公告)号：US08577948B2

    公开(公告)日：2013-11-05

    申请号：US12886012

    申请日：2010-09-20

    申请人： Suresh Srinivasan ,  Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Vasantha K. Erraguntla

    发明人： Suresh Srinivasan ,  Rajaraman Ramanarayanan ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  Vasantha K. Erraguntla

    IPC分类号： G06F7/483

    CPC分类号： G06F9/3893 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036

    摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及 如果差值大于阈值，则处理指令执行的第二路径。 基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。 描述和要求保护其他实施例。

    Dual Composite Field Advanced Encryption Standard Memory Encryption Engine
    8.
    发明申请
    Dual Composite Field Advanced Encryption Standard Memory Encryption Engine 审中-公开
    双复合现场高级加密标准内存加密引擎

    公开(公告)号：US20140229741A1

    公开(公告)日：2014-08-14

    申请号：US13993545

    申请日：2011-12-30

    申请人： Sanu K. Mathew ,  Shay Gueron ,  Ram K. Krishnamurthy

    发明人： Sanu K. Mathew ,  Shay Gueron ,  Ram K. Krishnamurthy

    IPC分类号： G06F21/72 ,  G06F21/60

    CPC分类号： G06F21/72 ,  G06F21/60 ,  H04L9/0631 ,  H04L2209/122

    摘要： A different set of polynomials may be selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.

    摘要翻译： 可以为加密和解密加速器选择不同的多项式集合。 也就是说，不同的多项式组用于加密和解密，每组被选择为使用较少的区域并为存储器加密引擎提供更多的功率。 这在一些实施例中是有利的，因为存储器读取操作通常比存储器写入更为关键和延迟敏感。

    USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION
    9.
    发明申请
    USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION 有权
    使用深色位置减少物理不可靠功能（PUF）错误率，而不会存储明显的位置

    公开(公告)号：US20150178143A1

    公开(公告)日：2015-06-25

    申请号：US14140243

    申请日：2013-12-24

    申请人： Sanu K. Mathew ,  Sudhir K. Satpathy ,  Patrick Koeberl ,  Jiangtao Li ,  Ram K. Krishnamurthy ,  Anand Rajan

    发明人： Sanu K. Mathew ,  Sudhir K. Satpathy ,  Patrick Koeberl ,  Jiangtao Li ,  Ram K. Krishnamurthy ,  Anand Rajan

    IPC分类号： G06F11/07

    CPC分类号： G06F11/0793 ,  G06F7/00 ,  G06F7/588 ,  G06F11/0745 ,  G11C7/24 ,  H04L9/3278 ,  H04L9/34

    摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.

    摘要翻译： 描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。 计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。 安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。 暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。 暗位表示PUF组件的PUF值在暗位窗口期间不稳定。 当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为 黑暗的一点

    Hybrid CAM assisted deflate decompression accelerator
    10.
    发明授权
    Hybrid CAM assisted deflate decompression accelerator 有权
    混合型CAM辅助减压加速器

    公开(公告)号：US09306596B2

    公开(公告)日：2016-04-05

    申请号：US14317698

    申请日：2014-06-27

    申请人： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Vinodh Gopal ,  Ram K. Krishnamurthy

    发明人： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Vinodh Gopal ,  Ram K. Krishnamurthy

    IPC分类号： H03M7/30 ,  H03M7/42 ,  G06F12/06 ,  G11C15/00 ,  G11C15/04

    CPC分类号： G06F12/0646 ,  G06F2212/1021 ,  G06F2212/401 ,  G11C15/00 ,  G11C15/04 ,  H03M7/3059 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40

    摘要： Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits.

    摘要翻译： 公开了一种集成电路，其包括包括第一部分和第二部分的存储器件。 第一部分是具有第一组单元的第一类型的内容可寻址存储器（CAM），并且第二部分是具有第二组单元格的第二类型的CAM。 第一组单元格小于第二组单元格。 集成电路还包括耦合到存储器件的解压加速器，解压加速器以产生多个长度代码。 多个长度码中的每一个包括至少一个位。 使用从包括多个符号的编码数据流接收的符号来生成多个长度码。 所述解压缩加速器进一步按照它们各自的位数按顺序将所述多个长度代码存储在所述存储器件的第一部分中。