公开(公告)号：US20100148269A1

公开(公告)日：2010-06-17

申请号：US12336544

申请日：2008-12-17

申请人： Ramachandramurthy Pradeep YELEHANKA ,  Shailendra MISHRA ,  Sripad NAGARAD

发明人： Ramachandramurthy Pradeep YELEHANKA ,  Shailendra MISHRA ,  Sripad NAGARAD

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/76837 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.

摘要翻译： 公开了一种包括具有有源区的衬底的器件。 该器件包括设置在有源区域中的栅极和栅极侧壁上的可调节侧壁间隔物。 可调节侧壁间隔物的轮廓包括上部和下部，其中上部中的间隔物的宽度以比下部更大的速率减小。

公开(公告)号：US6093602A

公开(公告)日：2000-07-25

申请号：US356007

申请日：1999-07-16

申请人： Weining Li ,  Lin Yung Tao ,  Ramachandramurthy Pradeep Yelehanka ,  Tin Tin Wee

发明人： Weining Li ,  Lin Yung Tao ,  Ramachandramurthy Pradeep Yelehanka ,  Tin Tin Wee

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/8242

CPC分类号： H01L27/11 ,  H01L21/76895 ,  H01L27/1104

摘要： A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.

摘要翻译： 已经实现了制造多孔体的局部互连的方法。 提供基板。 在衬底上提供窄间隔的特征，例如MOS晶体管栅极和多晶硅迹线。 沉积在衬底上的电介质层和狭窄间隔的特征。 对电介质层进行图案化以在狭缝间隔的特征之间形成开口，用于与衬底表面的规划接触。 沉积覆盖介质层并填充开口的掺杂多晶硅层。 掺杂的多晶硅层被蚀刻到窄间隔的特征的顶表面。 掺杂多晶硅层保留在狭窄间隔的特征之间的空间中。 覆盖窄间隔的特征和掺杂多晶硅层形成多晶硅化物层。 将多晶硅层和掺杂多晶硅层图案化以完成触点并产生多晶硅化物的局部互连，并且完成集成电路器件。

公开(公告)号：US08236678B2

公开(公告)日：2012-08-07

申请号：US12336544

申请日：2008-12-17

申请人： Ramachandramurthy Pradeep Yelehanka ,  Shailendra Mishra ,  Sripad Nagarad

发明人： Ramachandramurthy Pradeep Yelehanka ,  Shailendra Mishra ,  Sripad Nagarad

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/76837 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.

摘要翻译： 公开了一种包括具有有源区的衬底的器件。 该器件包括设置在有源区域中的栅极和栅极侧壁上的可调节侧壁间隔物。 可调节侧壁间隔物的轮廓包括上部和下部，其中上部中的间隔物的宽度以比下部更大的速率减小。