公开(公告)号：US6093602A

公开(公告)日：2000-07-25

申请号：US356007

申请日：1999-07-16

申请人： Weining Li ,  Lin Yung Tao ,  Ramachandramurthy Pradeep Yelehanka ,  Tin Tin Wee

发明人： Weining Li ,  Lin Yung Tao ,  Ramachandramurthy Pradeep Yelehanka ,  Tin Tin Wee

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/8242

CPC分类号： H01L27/11 ,  H01L21/76895 ,  H01L27/1104

摘要： A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.

摘要翻译： 已经实现了制造多孔体的局部互连的方法。 提供基板。 在衬底上提供窄间隔的特征，例如MOS晶体管栅极和多晶硅迹线。 沉积在衬底上的电介质层和狭窄间隔的特征。 对电介质层进行图案化以在狭缝间隔的特征之间形成开口，用于与衬底表面的规划接触。 沉积覆盖介质层并填充开口的掺杂多晶硅层。 掺杂的多晶硅层被蚀刻到窄间隔的特征的顶表面。 掺杂多晶硅层保留在狭窄间隔的特征之间的空间中。 覆盖窄间隔的特征和掺杂多晶硅层形成多晶硅化物层。 将多晶硅层和掺杂多晶硅层图案化以完成触点并产生多晶硅化物的局部互连，并且完成集成电路器件。

公开(公告)号：US06177304B1

公开(公告)日：2001-01-23

申请号：US09298933

申请日：1999-04-26

申请人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

发明人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823481

摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. Gate electrodes and associated source and drain regions are formed on and in the semiconductor substrate wherein the gate electrodes have silicon nitride sidewall spacers. A metal silicide layer is formed on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source and drain regions associated with the gate electrodes using a salicide process. A poly-cap layer is deposited overlying the substrate. The poly-cap layer is selectively removed overlying one of the salicided source and drain regions where a self-aligned contact is to be formed, and overlying another of the salicided source and drain regions and a portion of its associated salicided gate electrode where a butted contact is to be formed. An insulating layer is deposited over the surface of the semiconductor substrate. The insulating layer is etched through to form simultaneously the planned self-aligned contact opening and the planned butted contact opening. The self-aligned contact opening and the butted contact opening are filled with a conducting layer to complete fabrication of the integrated circuit device.

摘要翻译： 描述了在具有嵌入式存储器的逻辑电路的制造中整合自杀化和自对准接触过程的方法。 隔离区域形成在围绕并电隔离器件区域的半导体衬底上。 栅极电极和相关的源极和漏极区域形成在半导体衬底上和栅极中具有氮化硅侧壁间隔物。 使用自对准硅化物工艺在栅电极的顶表面和半导体衬底的顶表面上形成金属硅化物层，覆盖与栅电极相关的源极和漏极区域。 多层覆盖层沉积在衬底上。 选择性地去除聚盖层，覆盖其中要形成自对准接触的水银源区和漏区之一，并且覆盖另一个水银源和漏区及其相关联的盐化栅极的一部分，其中对接 接触将被形成。 绝缘层沉积在半导体衬底的表面上。 绝缘层被蚀刻通过以形成计划的自对准接触开口和计划的对接接触开口。 自对准的接触开口和对接的接触开口填充有导电层，以完成集成电路器件的制造。

公开(公告)号：US08261034B1

公开(公告)日：2012-09-04

申请号：US12638205

申请日：2009-12-15

申请人： Weining Li

发明人： Weining Li

IPC分类号： G06F12/00

CPC分类号： G06T1/20 ,  G06T1/60

摘要： A method for moving data in a memory system of a cascading region-based filter is disclosed. The method generally includes steps (A) to (C). Step (A) may load a first portion of the data from a buffer to the memory system at a start of a given cycle using a control circuit. The memory system generally has multiple first memories. A first region of a particular first memory may receive the first portion of data. Step (B) may copy the data in a second region of the particular first memory to a third region of the particular first memory at an end of the given cycle. Step (C) may copy the data in an output region of the particular first memory to an input region of a next first memory at the end of the given cycle. The output region generally overlaps both the first region and the second region.

摘要翻译： 公开了一种用于在基于级联区域的滤波器的存储器系统中移动数据的方法。 该方法通常包括步骤（A）至（C）。 步骤（A）可以使用控制电路在给定周期的开始时将数据的第一部分从缓冲器加载到存储器系统。 存储器系统通常具有多个第一存储器。 特定第一存储器的第一区域可以接收第一部分数据。 在给定周期结束时，步骤（B）可将特定第一存储器的第二区域中的数据复制到特定第一存储器的第三区域。 步骤（C）可以在给定周期结束时将特定第一存储器的输出区域中的数据复制到下一个第一存储器的输入区域。 输出区域通常与第一区域和第二区域重叠。

公开(公告)号：US08236646B2

公开(公告)日：2012-08-07

申请号：US10703289

申请日：2003-11-06

申请人： Tze Ho Simon Chan ,  Weining Li ,  Elgin Quek ,  Jia Zhen Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

发明人： Tze Ho Simon Chan ,  Weining Li ,  Elgin Quek ,  Jia Zhen Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76237 ,  H01L27/115 ,  H01L29/66825

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。 植入的源极区域形成在有源区域的一侧的沟槽中的一个中。 在有源区的另一侧的另一个沟槽中形成注入的漏极区。 然后在沟槽中形成浅沟槽隔离。 在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。

公开(公告)号：US07285804B2

公开(公告)日：2007-10-23

申请号：US11077731

申请日：2005-03-10

申请人： Elgin Quek ,  Jia Zhen Zheng ,  Pradeep R. Yelehanka ,  Weining Li

发明人： Elgin Quek ,  Jia Zhen Zheng ,  Pradeep R. Yelehanka ,  Weining Li

IPC分类号： H01L21/332

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/66378 ,  H01L29/66393 ,  H01L29/66795

摘要： An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

摘要翻译： 集成电路结构包括在半导体衬底的顶部上的半导体衬底和水平半导体鳍片。 存取晶体管栅极和晶闸管栅极位于半导体衬底的顶部并且与水平半导体鳍片接触。 存取晶体管是水平半导体鳍片和存取晶体管栅极的至少一部分。 晶闸管是水平半导体鳍片和晶闸管栅极的至少一部分，存取晶体管与晶闸管接触。

公开(公告)号：US07067362B2

公开(公告)日：2006-06-27

申请号：US10689923

申请日：2003-10-17

申请人： Tommy Lai ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zhen Zheng ,  Weining Li

发明人： Tommy Lai ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zhen Zheng ,  Weining Li

IPC分类号： H01L21/337

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31155 ,  H01L21/3144 ,  H01L27/1052 ,  H01L27/11546

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。 在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。

公开(公告)号：US20050026337A1

公开(公告)日：2005-02-03

申请号：US10628912

申请日：2003-07-28

申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L29/66393 ,  H01L27/11

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P—N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US06521540B1

公开(公告)日：2003-02-18

申请号：US09345357

申请日：1999-07-01

申请人： Weining Li

发明人： Weining Li

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76832

摘要： An improved and new process for fabricating self-aligned contacts (SAC) to source/drain areas of complimentary (CMOS) FET's has been developed using a non-conformal layer of silicon nitride, eliminating the need for a hard mask. This process allows for “zero” spacing from contact structure to polysilicon gate structure, for closely spaced design rule gates. Some key process features of this invention are as follows: no hard mask is needed and the gate process is exactly the same as “standard” logic process. The process differences are that between the S/D implant, salicidation and the normal contact process, there is inserted a non-conformal CVD silicon nitride deposition with a SAC pattern and etch process. The process is fully compatible with both state of-the-art salicide and polycide processes. The self-aligned contact process simplifies processing, while yielding improvements in electrical device performance and reliability. The process is very useful for the “standard” logic device salicided processes.

摘要翻译： 已经开发了使用非保形层氮化硅制造自对准接触（SAC）到互补（CMOS）FET的源极/漏极区域的改进和新工艺，从而消除了对硬掩模的需要。 该过程允许从接触结构到多晶硅栅极结构的“零”间隔，用于紧密间隔的设计规则栅极。 本发明的一些关键过程特征如下：不需要硬掩模，并且门过程与“标准”逻辑过程完全相同。 工艺差异在于在S / D植入物，盐化和正常接触过程之间，插入具有SAC图案和蚀刻工艺的非保形CVD氮化硅沉积。 该过程完全兼容最先进的杀虫剂和多杀菌剂过程。 自对准接触过程简化了处理，同时提高了电气设备的性能和可靠性。 该过程对于“标准”逻辑器件浸水过程非常有用。

公开(公告)号：US06509264B1

公开(公告)日：2003-01-21

申请号：US09537480

申请日：2000-03-30

申请人： Weining Li ,  Yung Tao Lin

发明人： Weining Li ,  Yung Tao Lin

IPC分类号： H01L2144

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L29/665

摘要： A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions. The integrated circuit device is annealed to react the metal layer and the polysilicon layer and silicon to selectively form a silicide layer in the surface of the polysilicon layer and in the surface of the semiconductor substrate at the contact surfaces. The remaining metal layer is removed to complete the device.

摘要翻译： 已经实现了用自对准硅化物形成MOS晶体管的新方法。 在半导体衬底上形成栅氧化层。 沉积多晶硅层。 图案化多晶硅层和栅极氧化层以形成栅极。 植入离子以形成轻掺杂的漏极区。 沉积介电层。 将电介质层抛光以露出栅极的顶表面。 然后将介电层各向异性地向下蚀刻以形成电介质侧壁间隔物。 电介质侧壁间隔物在露出栅极的垂直侧壁的一部分的同时覆盖栅极的垂直侧壁的一部分。 植入离子以形成源区和漏区。 沉积金属层。 在金属层之间形成接触表面，其中：暴露的栅极顶表面，栅极的垂直侧壁的暴露部分以及暴露的源极和漏极区域。 对集成电路器件进行退火以使金属层和多晶硅层和硅反应以在多晶硅层的表面和接触表面的半导体衬底的表面中选择性地形成硅化物层。 去除剩余的金属层以完成该装置。

公开(公告)号：US07183590B2

公开(公告)日：2007-02-27

申请号：US11422560

申请日：2006-06-06

申请人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

发明人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L29/74

CPC分类号： H01L27/11 ,  H01L27/0617 ,  H01L29/66393 ,  H01L29/7436

摘要： An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

摘要翻译： 集成电路结构包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。