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1.发明授权Controlling depth and latency of exit of a virtual processor's idle state in a power management environment 有权在电源管理环境中控制虚拟处理器空闲状态退出的深度和延迟公开(公告)号：US09027021B2
公开(公告)日：2015-05-05
申请号：US13445051
申请日：2012-04-12
申请人： Richard L. Arndt , Naresh Nayar , Christopher Francois , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg
发明人： Richard L. Arndt , Naresh Nayar , Christopher Francois , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg
CPC分类号： G06F9/45533 , G06F9/45541 , G06F2009/45575
摘要： A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
摘要翻译： 在逻辑分区的数据处理系统中提供一种机制，用于控制虚拟处理器的空闲状态的退出的深度和等待时间。 一个虚拟化层产生一个雪松延迟设置信息（CLSI）数据。 响应于引导逻辑分区，虚拟化层将CLSI数据传送到逻辑分区的操作系统（OS）。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。 响应于调用虚拟化层的OS，OS将虚拟处理器的特定空闲状态传送到虚拟化层，以将特定的空闲状态和唤醒特性分配给虚拟处理器。
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公开(公告)号：US08516484B2
公开(公告)日：2013-08-20
申请号：US12024466
申请日：2008-02-01
IPC分类号： G06F9/46
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译： 为数据处理系统提供了一个唤醒机制。 当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。 线程然后进入休眠状态直到事件发生。 唤醒阵列可以是内容可寻址存储器（CAM）。 当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。 操作系统或后台睡眠线程将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。
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3.发明授权Non-uniform memory access (NUMA) enhancements for shared logical partitions 失效共享逻辑分区的非均匀内存访问（NUMA）增强功能公开(公告)号：US08490094B2
公开(公告)日：2013-07-16
申请号：US12394669
申请日：2009-02-27
申请人： Vaijayanthimala K. Anand , Mark R. Funk , Steven R. Kunkel , Mysore S. Srinivas , Randal C. Swanberg , Ronald D. Young
发明人： Vaijayanthimala K. Anand , Mark R. Funk , Steven R. Kunkel , Mysore S. Srinivas , Randal C. Swanberg , Ronald D. Young
CPC分类号： G06F9/5077 , G06F2212/2542
摘要： In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.
摘要翻译： 在包含多个节点和多个逻辑分区的NUMA拓扑计算机系统中，其中一些可能是专用的，其他的可以是共享的，而在共享逻辑分区中启用了NUMA优化。 这是通过在分配给逻辑分区的每个虚拟处理器中指定家庭节点参数来完成的。 当由共享逻辑分区中的操作系统创建任务时，将家庭节点分配给该任务，并且操作系统尝试将该任务分配给具有与该任务的家庭节点匹配的家庭节点的虚拟处理器 。 然后，分区管理器尝试将虚拟处理器分配给其对应的家庭节点。 如果可以这样做，可以执行NUMA优化，而不会降低共享逻辑分区的性能。
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4.发明授权Processor and memory folding for managing power consumption in information processing systems 失效处理器和内存折叠，用于管理信息处理系统中的功耗公开(公告)号：US08381005B2
公开(公告)日：2013-02-19
申请号：US12642098
申请日：2009-12-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： A method, system and computer-usable medium are disclosed for managing power consumption in information processing systems. Processing resources are successively folded, allowing them to be placed into deeper and deeper power saving states while maintaining the ability to respond to new processing loads without exposing the latency of the deeper power saving states as they are unfolded. Before a deeper power saving state can be used, there must be sufficient processing resources in the prior power saving state to mask the latency of bringing a processing resource out of the deeper power saving state.
摘要翻译： 公开了一种用于管理信息处理系统中的功耗的方法，系统和计算机可用介质。 处理资源被连续地折叠，使得它们能够被放置在更深和更深的省电状态，同时保持对新的处理负载的响应能力，而不会暴露更深的省电状态在其展开时的延迟。 在可以使用更深的省电状态之前，在现有的省电状态下必须有足够的处理资源，以掩盖使处理资源脱离更深的省电状态的延迟。
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公开(公告)号：US08312458B2
公开(公告)日：2012-11-13
申请号：US12024384
申请日：2008-02-01
摘要： A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.
摘要翻译： 提供了一个唤醒机制，具有用于多处理器数据处理系统的中央存储库唤醒阵列。 唤醒机制识别一种编程习语，其指示在多处理器数据处理系统中的处理器上运行的线程正在等待事件。 唤醒机制更新了具有与事件相关联的目标地址的中央存储库唤醒数组。 中央存储库唤醒阵列中的每个条目可以包括线程标识（ID），中央处理单元（CPU）ID，目标地址，预期数据，比较类型，锁定位，优先级和 线程状态指针，其是存储线程状态信息的地址。
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6.发明授权公开(公告)号：US08176487B2
公开(公告)日：2012-05-08
申请号：US12110953
申请日：2008-04-28
IPC分类号： G06F9/455
CPC分类号： G06F12/1475 , G06F9/45558 , G06F12/1491 , G06F2009/45579 , G06F2212/1056
摘要： A method in a data processing system is provided for processing a service request of a client partition. The method includes: obtaining by a service partition of the data processing system the service request from the client partition, wherein both the client and service partitions execute above a hypervisor of the data processing system; and processing the service request by the service partition utilizing a processor quantum assigned to the client partition and donated by the client partition to the service partition. The client partition controls scheduling of the service partition by queuing the service request at the client partition until the client partition decides to proceed with execution of the service request by the service partition. In one implementation, the service partition is a partition adjunct of the data processing system, which utilizes donated virtual address space of the client partition.
摘要翻译： 提供数据处理系统中的方法来处理客户端分区的服务请求。 该方法包括：通过数据处理系统的服务分区获取来自客户端分区的服务请求，其中客户端和服务分区都在数据处理系统的管理程序之上执行; 以及使用分配给所述客户端分区并由所述客户端分区捐赠给所述服务分区的处理器量化由所述服务分区处理所述服务请求。 客户机分区通过在客户端分区排队服务请求来控制服务分区的调度，直到客户端分区决定继续执行服务分区的服务请求。 在一个实现中，服务分区是数据处理系统的分区附件，其利用客户端分区的捐赠的虚拟地址空间。
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公开(公告)号：US08145849B2
公开(公告)日：2012-03-27
申请号：US12024204
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F9/382 , G06F9/3851 , G06F9/528 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity.
摘要翻译： 为数据处理系统提供了一个唤醒机制。 唤醒机制被配置为在系统总线上发出预先加载命令以从目标地址读取数据值并执行比较操作以确定目标地址上的数据值是否指示用于 一个线程正在等待发生。 响应于比较导致事件未发生的确定，唤醒引导器填充具有目标地址的唤醒存储阵列并且在系统总线上窥探目标地址而没有数据独占性。 响应于导致确定事件已经发生的比较，唤醒引导器在系统总线上发出加载命令以从具有数据排他性的目标地址读取数据值。
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公开(公告)号：US08145723B2
公开(公告)日：2012-03-27
申请号：US12424983
申请日：2009-04-16
IPC分类号： G06F15/16
CPC分类号： G06F9/5044 , G06F9/3009 , G06F2209/509
摘要： A remote update programming idiom accelerator is configured to detect a complex remote update programming idiom in an instruction sequence of a thread. The complex remote update programming idiom includes a read operation for reading data from a storage location at a remote node, a sequence of instructions for performing an update operation on the data to form result data, and a write operation for writing the result data to the storage location at the remote node. The remote update programming idiom accelerator is configured to determine whether the sequence of instructions is longer than an instruction size threshold and responsive to a determination that the sequence of instructions is not longer than the instruction size threshold, transmit the complex remote update programming idiom to the remote node to perform the update operation on the data at the remote node.
摘要翻译： 远程更新编程习惯加速器被配置为检测线程的指令序列中的复杂的远程更新编程习语。 复杂的远程更新编程习语包括用于从远程节点的存储位置读取数据的读取操作，用于对数据执行更新操作以形成结果数据的指令序列，以及用于将结果数据写入到 远程节点的存储位置。 远程更新编程习惯加速器被配置为确定指令序列是否长于指令大小阈值，并且响应于指令序列不长于指令大小阈值的确定，将复杂的远程更新编程成语发送到 远程节点对远程节点上的数据执行更新操作。
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公开(公告)号：US20110173632A1
公开(公告)日：2011-07-14
申请号：US12024703
申请日：2008-02-01
IPC分类号： G06F9/46
摘要： A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism performs a look-ahead polling operation for each of the programming idioms. If each of the look-ahead polling operations fails, then the wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom.
摘要翻译： 为数据处理系统提供硬件唤醒机制。 唤醒机制在用于编程习惯的线程中前进，表示线程正在等待事件。 唤醒机制为每个编程习语执行预先轮询操作。 如果每个先行轮询操作失败，则唤醒机制将使用与每个识别的编程习语的事件相关联的目标地址来更新唤醒数组。
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公开(公告)号：US20110173631A1
公开(公告)日：2011-07-14
申请号：US12024466
申请日：2008-02-01
IPC分类号： G06F9/46
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译： 为数据处理系统提供了一个唤醒机制。 当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。 线程然后进入休眠状态直到事件发生。 唤醒阵列可以是内容可寻址存储器（CAM）。 当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。 操作系统或后台睡眠线程将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。
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