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    SYSTEM AND METHOD FOR USING NETWORK INTERFACE CARD RESET PIN AS INDICATION OF LOCK LOSS OF A PHASE LOCKED LOOP AND BROWNOUT CONDITION
    1.
    发明申请
    SYSTEM AND METHOD FOR USING NETWORK INTERFACE CARD RESET PIN AS INDICATION OF LOCK LOSS OF A PHASE LOCKED LOOP AND BROWNOUT CONDITION 有权
    使用网络接口卡复位PIN作为相位锁定环路和布朗状态的锁定丢失的指示的系统和方法

    公开(公告)号：US20080071959A1

    公开(公告)日：2008-03-20

    申请号：US11934203

    申请日：2007-11-02

    申请人： THOMAS DAVID ,  RANDALL SEARS

    发明人： THOMAS DAVID ,  RANDALL SEARS

    IPC分类号： G06F13/24

    CPC分类号： G06F13/387

    摘要： A method for providing an indication from a network interface controller to a microcontroller is disclosed wherein upon occurrence of a particular condition within the network interface controller, an indication is provided from a reset pin of the network interface controller to the microcontroller unit. Upon receipt of the indication by the microcontroller unit, communications between the network interface controller and the microcontroller unit are inhibited.

    摘要翻译： 公开了一种从网络接口控制器向微控制器提供指示的方法，其中当在网络接口控制器内发生特定状况时，从网络接口控制器的复位引脚向微控制器单元提供指示。 在微控制器单元接收到指示时，禁止了网络接口控制器和微控制器单元之间的通信。

    Parallel to USB bridge controller
    2.
    发明申请
    Parallel to USB bridge controller 审中-公开
    并联USB桥控制器

    公开(公告)号：US20060149870A1

    公开(公告)日：2006-07-06

    申请号：US11026989

    申请日：2004-12-30

    申请人： Randall Sears ,  David Mervine ,  Paul Highley

    发明人： Randall Sears ,  David Mervine ,  Paul Highley

    IPC分类号： G06F13/38

    CPC分类号： G06F13/4027 ,  G06F13/385

    摘要： A parallel to USB bridge controller includes a USB transceiver for transmitting and receiving on a USB link and a serial interface engine connected to the USB link for converting between USB protocol and serial interface protocol. A memory interface within the controller includes a transmit data register for receiving data from a parallel data link and a receive register for receiving data to be transmitted over the parallel data link. The transmit data register and the receive data register of the memory interface are located within the memory space of a processor connected to the USB serial interface. The memory interface is able to send and receive data between the transmit and receive data registers and an external processor over the parallel data link.

    摘要翻译： 与USB桥接控制器的并行连接器包括USB收发器，用于在USB链路上发送和接收，以及连接到USB链路的串行接口引擎，用于在USB协议和串行接口协议之间进行转换。 控制器内的存储器接口包括用于从并行数据链路接收数据的发送数据寄存器和用于接收要通过并行数据链路发送的数据的接收寄存器。 存储器接口的发送数据寄存器和接收数据寄存器位于连接到USB串行接口的处理器的存储器空间内。 存储器接口能够通过并行数据链路在发送和接收数据寄存器与外部处理器之间发送和接收数据。

    Ethernet controller with excess on-board flash for microcontroller interface
    3.
    发明申请
    Ethernet controller with excess on-board flash for microcontroller interface 有权

    公开(公告)号：US20060002210A1

    公开(公告)日：2006-01-05

    申请号：US10880921

    申请日：2004-06-30

    申请人： Thomas David ,  Paul Highley ,  Randall Sears

    发明人： Thomas David ,  Paul Highley ,  Randall Sears

    IPC分类号： G11C7/00

    CPC分类号： H04L12/40013 ,  H04L49/90 ,  H04L49/901

    摘要： A single chip network controller for interfacing between a physical network and a processing system on the media side of the network controller. The network controller includes a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and decoding the received data. A media layer is provided for interfacing with the processing system for receiving data from the processing system for interface with the physical layer for encoding and transmission thereof and for receiving decoded data from the physical layer and providing access thereto by the processing system. An on-chip non-volatile memory is provided having a first portion associated with configuration information for configuring the operation of the physical layer and the media layer, and a second portion thereof that is accessible by the processing system on the media side of the network controller. A memory interface allows the processing system to interface with the second portion of the memory, such that the processing system has an expanded memory capability.