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公开(公告)号：US20080256379A1
公开(公告)日：2008-10-16
申请号：US11786125
申请日：2007-04-11
IPC分类号： G06F1/06
CPC分类号： G06F1/10
摘要： In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.
摘要翻译： 在一个实施例中，计算机系统至少包括第一计算单元和第二计算单元，每个计算单元包括至少一个处理器，耦合第一和第二计算单元的路由设备，耦合到第一计算单元的全局时钟信号源 至少两个计算单元以产生全局时钟信号，至少一个定时管理器产生定时控制信号，其中所述至少两个计算单元包括本地振荡器以产生本地时钟信号，以及多路复用器，用于接收全局时钟信号 时钟信号，本地时钟信号和定时控制信号，并且响应于控制信号输出全局时钟信号或本地时钟信号之一。
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公开(公告)号：US20080080566A1
公开(公告)日：2008-04-03
申请号：US11540244
申请日：2006-09-29
IPC分类号： H04J3/06
CPC分类号： G06F1/12
摘要： There is provided a method of operating a computer system. The computer system comprises at least two cabinets and the at least two cabinets have at least one clock signal. The method includes selecting one of the at least one clock signal to serve as a master signal, and synchronizing the computer system to operate from the master signal. Additionally, the method includes altering the capacity of the system while the system is operating.
摘要翻译： 提供了一种操作计算机系统的方法。 所述计算机系统包括至少两个机柜，并且所述至少两个机柜具有至少一个时钟信号。 该方法包括选择至少一个时钟信号中的一个作为主信号，并使计算机系统与主信号同步工作。 此外，该方法包括在系统运行时改变系统的容量。
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公开(公告)号：US08799700B2
公开(公告)日：2014-08-05
申请号：US13379276
申请日：2009-07-31
申请人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
发明人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
CPC分类号： G06F11/1604 , G06F1/10 , G06F11/004 , G06F11/20
摘要： To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.
摘要翻译： 为了提供容错的扩频时钟信号，提供了具有各自扩频控制电路的多个处理模块。 冗余时钟源的时钟信号被提供给多个处理模块。 故障转移控制逻辑从冗余时钟源中选择相应的一个时钟信号，以在每个处理模块中使用。 在多个处理模块中的至少一些处理模块的每一个中对相应的所选择的时钟信号施加频率扩展。
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公开(公告)号：US20120117415A1
公开(公告)日：2012-05-10
申请号：US13379276
申请日：2009-07-31
申请人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
发明人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
IPC分类号： G06F1/08
CPC分类号： G06F11/1604 , G06F1/10 , G06F11/004 , G06F11/20
摘要： To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.
摘要翻译： 为了提供容错的扩频时钟信号，提供了具有各自扩频控制电路的多个处理模块。 冗余时钟源的时钟信号被提供给多个处理模块。 故障转移控制逻辑从冗余时钟源中选择相应的一个时钟信号，以便在每个处理模块中使用。 在多个处理模块中的至少一些处理模块的每一个中对相应的所选择的时钟信号施加频率扩展。
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公开(公告)号：US4245186A
公开(公告)日：1981-01-13
申请号：US968068
申请日：1978-12-11
CPC分类号： H03J3/185
摘要： A high input impedance, low output impedance, temperature-stable tuning voltage interface circuit with substantial ripple rejection and negligible DC offset. The circuit comprises two transistors of opposite conductivity types, the first being coupled through a resistor to a supply voltage and through a temperature-stabilizing, DC-offsetting diode to the output of the second transistor. The rejection of the ripple voltage superimposed on the supply voltage is determined by the ratio of the value of the resistor to the effective resistance of the diode.
摘要翻译： 高输入阻抗，低输出阻抗，温度稳定的调谐电压接口电路，具有显着的纹波抑制和可忽略的直流偏移。 电路包括两个相反导电类型的晶体管，第一个通过电阻器耦合到电源电压，并通过温度稳定的DC偏置二极管耦合到第二晶体管的输出端。 叠加在电源电压上的纹波电压的抑制取决于电阻值与二极管的有效电阻的比值。
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公开(公告)号：US4027252A
公开(公告)日：1977-05-31
申请号：US640010
申请日：1975-12-12
申请人： Rangaswamy Arumugham
发明人： Rangaswamy Arumugham
CPC分类号： H03J7/10
摘要： A tuning voltage circuit for providing a tuning voltage which is corrected by an automatic frequency control error voltage for application to a voltage controlled radio frequency tuning means for a television receiver is shown. The voltage controlled radio frequency tuning means has a non-linear frequency versus tuning voltage characteristic which causes the sensitivity of the tuning means to the error voltage to vary over the frequency range of interest. The tuning voltage circuit includes a high impedance tuning voltage source which provides sensitivity compensation for the automatic frequency control error voltage to compensate for variations of the automatic frequency control pull-in range in the frequency range of interest.
摘要翻译： 示出了用于提供由自动频率控制误差电压校正的调谐电压的调谐电压电路，用于应用于电视接收机的压控射频调谐装置。 电压控制射频调谐装置具有非线性频率对调谐电压特性，其使得调谐装置的灵敏度在误差电压上在感兴趣的频率范围内变化。 调谐电压电路包括高阻抗调谐电压源，其为自动频率控制误差电压提供灵敏度补偿，以补偿感兴趣的频率范围内的自动频率控制拉入范围的变化。
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公开(公告)号：US07809025B2
公开(公告)日：2010-10-05
申请号：US11540244
申请日：2006-09-29
IPC分类号： H04J3/06
CPC分类号： G06F1/12
摘要： There is provided a method of operating a computer system. The computer system comprises at least two cabinets and the at least two cabinets have at least one clock signal. The method includes selecting one of the at least one clock signal to serve as a master signal, and synchronizing the computer system to operate from the master signal. Additionally, the method includes altering the capacity of the system while the system is operating.
摘要翻译： 提供了一种操作计算机系统的方法。 所述计算机系统包括至少两个机柜，并且所述至少两个机柜具有至少一个时钟信号。 该方法包括选择至少一个时钟信号中的一个作为主信号，并使计算机系统与主信号同步工作。 此外，该方法包括在系统运行时改变系统的容量。
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公开(公告)号：US4290005A
公开(公告)日：1981-09-15
申请号：US166526
申请日：1980-07-07
申请人： Rangaswamy Arumugham
发明人： Rangaswamy Arumugham
摘要： A compensated reference voltage source for providing a stable output voltage despite variations in operating voltage. The circuitry includes a series arrangement of a first resistance, a Zener diode, and a second resistance connected between a source of operating voltage and ground. A first transistor has its collector connected to the juncture of the first resistance and the Zener diode, its base connected to the juncture of the Zener diode and the second resistance, and its emitter connected to ground. A second transistor has its base and emitter connected directly to the corresponding electrodes of the first transistor and its collector connected to an output terminal. A third transistor has its collector connected to the source of operating voltage, its emitter connected to the output terminal, and its base connected to the collector of the first transistor. The base-emitter characteristics of the transistors are essentially identical. The voltage across the Zener diode remains constant despite variations in the operating voltage. However, the voltage at the collector of the first transistor varies because of changes in current flow across its base-emitter junction. Because of the interconnections, equal currents flow through each of the transistors. Since the base-emitter characteristics of the transistors are identical, the voltage drops across the base-emitter junctions of the first and third transistors are equal. Thus, the voltage at the output terminal is equal to the voltage across the Zener diode and remains constant despite variations in the operating voltage.
摘要翻译： 补偿参考电压源，尽管工作电压有变化，但仍可提供稳定的输出电压。 电路包括串联的第一电阻，齐纳二极管和连接在工作电压源和地之间的第二电阻。 第一晶体管的集电极连接到第一电阻和齐纳二极管的接合点，其基极连接到齐纳二极管和第二电阻的接合端，其发射极连接到地。 第二晶体管的基极和发射极直接连接到第一晶体管的相应电极，其集电极连接到输出端。 第三晶体管的集电极连接到工作电压源，其发射极连接到输出端，其基极连接到第一晶体管的集电极。 晶体管的基极 - 发射极特性基本相同。 尽管工作电压有变化，齐纳二极管两端的电压保持不变。 然而，第一晶体管的集电极处的电压由于其基极 - 发射极结上的电流的变化而变化。 由于互连，相等的电流流过每个晶体管。 由于晶体管的基极 - 发射极特性相同，所以第一和第三晶体管的基极 - 发射极结两端的电压相等。 因此，输出端子处的电压等于齐纳二极管两端的电压，尽管工作电压有变化，但仍保持恒定。
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公开(公告)号：US4122493A
公开(公告)日：1978-10-24
申请号：US833759
申请日：1977-09-16
摘要： Circuitry compensating for inherent nonlinearities in the tuning voltage sensitivity of varactor tuners, thereby providing relatively constant AFC pull-in range throughout the band of operating frequencies, is shown. In both the VHF and UHF bands, the AFC system develops an error correction voltage in proportion to the tuning voltage. With respect to reception of VHF channels, a gain switching circuit operates to reduce the proportion of AFC error correction voltage developed on a High Band VHF channel, thereby compensating for increased tuning voltage sensitivity on High Band VHF. With respect to reception of UHF channels, a tuning voltage sensing circuit operates to effect an error correction voltage that is a greater proportion of the tuning voltage when the tuning voltage is above a pre-determined value corresponding to approximately channel 60.
摘要翻译： 示出了补偿变容二极管调谐器的调谐电压灵敏度中的固有非线性的电路，从而在整个工作频率带提供相对恒定的AFC拉入范围。 在VHF和UHF频段中，AFC系统与调谐电压成比例地产生纠错电压。 关于VHF信道的接收，增益切换电路用于降低在高频带VHF信道上产生的AFC误差校正电压的比例，从而补偿在高频带VHF上提高的调谐电压灵敏度。 关于UHF通道的接收，调谐电压感测电路操作以实现当调谐电压高于对应于大约通道60的预定值时调谐电压的较大比例的纠错电压。
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公开(公告)号：US07814301B2
公开(公告)日：2010-10-12
申请号：US11786125
申请日：2007-04-11
IPC分类号： G06F9/00
CPC分类号： G06F1/10
摘要： In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.
摘要翻译： 在一个实施例中，计算机系统至少包括第一计算单元和第二计算单元，每个计算单元包括至少一个处理器，耦合第一和第二计算单元的路由设备，耦合到第一计算单元的全局时钟信号源 至少两个计算单元以产生全局时钟信号，至少一个定时管理器产生定时控制信号，其中所述至少两个计算单元包括本地振荡器以产生本地时钟信号，以及多路复用器，用于接收全局时钟信号 时钟信号，本地时钟信号和定时控制信号，并且响应于控制信号输出全局时钟信号或本地时钟信号之一。
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