公开(公告)号：US20120124261A1

公开(公告)日：2012-05-17

申请号：US12946699

申请日：2010-11-15

申请人： Alain Vergnes ,  Renaud Tiennot ,  Guillaume Pean

发明人： Alain Vergnes ,  Renaud Tiennot ,  Guillaume Pean

IPC分类号： G06F13/36 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.

摘要翻译： 微控制器包括用于连接各种模块的系统总线矩阵。 微控制器还包括模块之间的直接连接。 例如，微控制器可以包括数据处理模块和存储器控制器模块之间的直接连接，以提高由数据处理模块处理的数据的传输速率。

公开(公告)号：US20100262880A1

公开(公告)日：2010-10-14

申请号：US12421348

申请日：2009-04-09

申请人： Alain Vergnes ,  Renaud Tiennot

发明人： Alain Vergnes ,  Renaud Tiennot

IPC分类号： H03M13/00 ,  G06F11/07

CPC分类号： H02P31/00

摘要： The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.

摘要翻译： 所公开的用于电动机控制的正交解码器滤波电路使用一个正交信号来校正另一个正交信号中的误差，从而允许由于大的灰尘颗粒或划痕而产生的噪声信号被恢复。 在一些实现中，用于正交信号的系统处理包括由第一正交信号的边缘触发的第一电路，以在第一正交信号的连续边缘期间检测第二正交信号的不活动。 第二电路可操作以在第二正交信号的不活动期间对第一正交信号的连续边缘的数量进行计数。 第三电路可操作以在由第二电路的计数值确定的时间段期间组合第一正交信号的转换与第二正交信号。

公开(公告)号：US08601197B2

公开(公告)日：2013-12-03

申请号：US12946699

申请日：2010-11-15

申请人： Alain Vergnes ,  Renaud Tiennot ,  Guillaume Pean

发明人： Alain Vergnes ,  Renaud Tiennot ,  Guillaume Pean

IPC分类号： G06F13/36

CPC分类号： G06F13/4022

摘要： A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.

摘要翻译： 微控制器包括用于连接各种模块的系统总线矩阵。 微控制器还包括模块之间的直接连接。 例如，微控制器可以包括数据处理模块和存储器控制器模块之间的直接连接，以提高由数据处理模块处理的数据的传输速率。

公开(公告)号：US20100241874A1

公开(公告)日：2010-09-23

申请号：US12406817

申请日：2009-03-18

申请人： Alain Vergnes ,  Renaud Tiennot

发明人： Alain Vergnes ,  Renaud Tiennot

IPC分类号： H04L9/06

CPC分类号： G06F21/71

摘要： A scrambler/descrambler module included in an integrated circuit device is operable for receiving a scrambling key and constant data that is unique to the integrated circuit device. The scrambler/descrambler module includes a first layer or circuit arrangement that uses a scrambling key to generate first scrambled data. The scrambler/descrambler module includes a second layer or second circuit arrangement that uses data that is unique to the integrated circuit device, and that is constant over the life of the integrated circuit device, to scramble the first scrambled data to generate second scrambled data.

摘要翻译： 包括在集成电路装置中的扰码器/解扰器模块可操作用于接收加扰密钥和集成电路设备唯一的恒定数据。 加扰器/解扰器模块包括使用加扰密钥生成第一加扰数据的第一层或电路装置。 加扰器/解扰器模块包括使用集成电路器件唯一的数据并且在集成电路器件的整个使用寿命期间恒定的第二层或第二电路装置，以加扰第一加扰数据以产生第二加扰数据。

公开(公告)号：US08745410B2

公开(公告)日：2014-06-03

申请号：US12406817

申请日：2009-03-18

申请人： Alain Vergnes ,  Renaud Tiennot

发明人： Alain Vergnes ,  Renaud Tiennot

IPC分类号： H04L29/06

CPC分类号： G06F21/71

摘要： A scrambler/descrambler module included in an integrated circuit device is operable for receiving a scrambling key and constant data that is unique to the integrated circuit device. The scrambler/descrambler module includes a first layer or circuit arrangement that uses a scrambling key to generate first scrambled data. The scrambler/descrambler module includes a second layer or second circuit arrangement that uses data that is unique to the integrated circuit device, and that is constant over the life of the integrated circuit device, to scramble the first scrambled data to generate second scrambled data.

摘要翻译： 包括在集成电路装置中的扰码器/解扰器模块可操作用于接收加扰密钥和集成电路设备唯一的恒定数据。 加扰器/解扰器模块包括使用加扰密钥生成第一加扰数据的第一层或电路装置。 加扰器/解扰器模块包括使用集成电路器件唯一的且在集成电路器件的整个使用寿命期间恒定的数据的第二层或第二电路装置，以加扰第一加扰数据以产生第二加扰数据。

公开(公告)号：US20070233429A1

公开(公告)日：2007-10-04

申请号：US11426528

申请日：2006-06-26

申请人： Alain Vergnes ,  Renaud Tiennot

发明人： Alain Vergnes ,  Renaud Tiennot

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： G06F21/71

摘要： An inappropriate-access module is incorporated in a computer system along with other computer system modules. The inappropriate-access module is connected to a read address decoder and controlling logic located within various other modules. The inappropriate-access module detects inappropriate read accesses or the occurrence of the inappropriate access during operations performed on related sensitive system resources in accompanying computer system modules. The inappropriate-access module produces an inappropriate-access flag, made available to the rest of the system, which invokes responses in the accompanying modules such as a halt in processing and protective measures for system resources. Additionally, a related logic block is able to detect the inappropriate access and produce an inappropriate-access trigger which causes a halt to processing within the logic block as well as in related system modules.

摘要翻译： 不合适的访问模块与其他计算机系统模块一起并入计算机系统中。 不正当访问模块连接到读地址解码器和位于各种其他模块内的控制逻辑。 不适当的访问模块在随附的计算机系统模块中对相关敏感系统资源执行的操作期间检测不适当的读取访问或发生不适当的访问。 不适当的访问模块产生不适当的访问标志，对系统的其余部分可用，其调用所附模块中的响应，例如处理中的停止和用于系统资源的保护措施。 另外，相关的逻辑块能够检测不适当的访问并产生不合适的访问触发器，这导致停止在逻辑块内以及在相关系统模块中的处理。

公开(公告)号：US20140281081A1

公开(公告)日：2014-09-18

申请号：US13840681

申请日：2013-03-15

申请人： Franck Lunadier ,  Eric Matulik ,  Renaud Tiennot

发明人： Franck Lunadier ,  Eric Matulik ,  Renaud Tiennot

IPC分类号： G06F13/368

CPC分类号： G06F13/362 ,  G06F13/368 ,  G06F13/4022 ,  G06F13/4068

摘要： A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

摘要翻译： 公开了一种多矩阵总线系统，其通过在网络传送请求路径中通过仲裁节点尽可能快地传播来自上游仲裁节点或主机的最高优先级值来提供主动服务质量（QoS） 当前总线请求在仲裁节点挂起。 总线系统确保任何最后一个下行仲裁节点在任何时候都知道网络传输请求路径中等待的最高优先级请求是来自正在竞争共享总线层交换机和仲裁节点的网络传输请求路径中的主机。

公开(公告)号：US08316017B2

公开(公告)日：2012-11-20

申请号：US11426528

申请日：2006-06-26

申请人： Alain Vergnes ,  Renaud Tiennot

发明人： Alain Vergnes ,  Renaud Tiennot

IPC分类号： G06F7/00 ,  G06F17/30 ,  G06F7/04 ,  G06F11/00

CPC分类号： G06F21/71

摘要： An inappropriate-access module is incorporated in a computer system along with other computer system modules. The inappropriate-access module is connected to a read address decoder and controlling logic located within various other modules. The inappropriate-access module detects inappropriate read accesses or the occurrence of the inappropriate access during operations performed on related sensitive system resources in accompanying computer system modules. The inappropriate-access module produces an inappropriate-access flag, made available to the rest of the system, which invokes responses in the accompanying modules such as a halt in processing and protective measures for system resources. Additionally, a related logic block is able to detect the inappropriate access and produce an inappropriate-access trigger which causes a halt to processing within the logic block as well as in related system modules.

摘要翻译： 不合适的访问模块与其他计算机系统模块一起并入计算机系统中。 不正当访问模块连接到读地址解码器和位于各种其他模块内的控制逻辑。 不适当的访问模块在随附的计算机系统模块中对相关敏感系统资源执行的操作期间检测不适当的读取访问或发生不适当的访问。 不适当的访问模块产生不适当的访问标志，对系统的其余部分可用，其调用所附模块中的响应，例如处理中的停止和用于系统资源的保护措施。 另外，相关的逻辑块能够检测不适当的访问并产生不合适的访问触发器，这导致停止在逻辑块内以及在相关系统模块中的处理。

公开(公告)号：US08190956B2

公开(公告)日：2012-05-29

申请号：US12421348

申请日：2009-04-09

申请人： Alain Vergnes ,  Renaud Tiennot

发明人： Alain Vergnes ,  Renaud Tiennot

IPC分类号： G06F11/00

CPC分类号： H02P31/00

摘要： The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.

摘要翻译： 所公开的用于电动机控制的正交解码器滤波电路使用一个正交信号来校正另一个正交信号中的误差，从而允许由于大的灰尘颗粒或划痕而产生的噪声信号被恢复。 在一些实现中，用于正交信号的系统处理包括由第一正交信号的边缘触发的第一电路，以在第一正交信号的连续边缘期间检测第二正交信号的不活动。 第二电路可操作以在第二正交信号的不活动期间对第一正交信号的连续边缘的数量进行计数。 第三电路可操作以在由第二电路的计数值确定的时间段期间组合第一正交信号的转换与第二正交信号。

公开(公告)号：US07689758B2

公开(公告)日：2010-03-30

申请号：US11776916

申请日：2007-07-12

申请人： Renaud Tiennot

发明人： Renaud Tiennot

IPC分类号： G06F13/36 ,  G06F13/20 ,  G06F13/00

CPC分类号： G06F13/387

摘要： A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix.

摘要翻译： 一种双总线矩阵架构，包括：连接到多个高性能外设并具有多个主端口和多个从端口的第一互连矩阵; 连接到多个有限带宽外围设备并具有多个主端口和多个从端口的第二互连矩阵; 以及连接到第一互连矩阵的一个（或多个）从属端口和第二互连矩阵的一个（或多个）主端口的共享多端口控制器，其中该共享多端口控制器控制对高性能外设的访问 以及带宽有限的外设，通过第一互连矩阵来引导对高性能外设的访问，并通过第二互连矩阵访问有限带宽的外设。