公开(公告)号：US07450458B2

公开(公告)日：2008-11-11

申请号：US11341717

申请日：2006-01-30

申请人： Yuki Mori ,  Renichi Yamada ,  Shuichi Tsukada ,  Kiyonori Oyu

发明人： Yuki Mori ,  Renichi Yamada ,  Shuichi Tsukada ,  Kiyonori Oyu

IPC分类号： G11C11/34

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/50016

摘要： The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.

摘要翻译： 本发明能够筛选所谓的可变保留时间（VRT）故障，即由于诸如随机电报噪声的数据保留时间的波动而在DRAM中发生的保留故障。 在芯片的所有存储单元上重复用于检查数据保留功能的暂停/刷新测试，使得可能发生由于数据保留能力的随机波动而发生的保留故障的存储单元被进行筛选。

公开(公告)号：US07247890B2

公开(公告)日：2007-07-24

申请号：US10931119

申请日：2004-09-01

申请人： Tomoko Sekiguchi ,  Shinichiro Kimura ,  Renichi Yamada ,  Kikuo Watanabe ,  Hiroshi Miki ,  Kenichi Takeda

发明人： Tomoko Sekiguchi ,  Shinichiro Kimura ,  Renichi Yamada ,  Kikuo Watanabe ,  Hiroshi Miki ,  Kenichi Takeda

IPC分类号： H01L31/0328 ,  H01L29/80

CPC分类号： H01L29/66659 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/1079 ,  H01L29/6656 ,  H01L29/7835

摘要： Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.

摘要翻译： 这里公开了具有在存储单元中具有MISFET阈值电压的较小散射并具有良好的电容保持性的DRAM的半导体器件，以及半导体器件的制造方法。 在光氧化之前，在栅电极的侧壁上形成抗氧化膜，从而抑制栅电极的侧壁的氧化，并且在不对称扩散区域结构中减少形成在侧壁上的膜的厚度的散射 使数据线一侧的n型半导体区域和p型半导体区域的杂质浓度比n型半导体区域和p型半导体区域的杂质浓度相对高于 电容器。

公开(公告)号：US20060203590A1

公开(公告)日：2006-09-14

申请号：US11341717

申请日：2006-01-30

申请人： Yuki Mori ,  Renichi Yamada ,  Shuichi Tsukada ,  Kiyonori Oyu

发明人： Yuki Mori ,  Renichi Yamada ,  Shuichi Tsukada ,  Kiyonori Oyu

IPC分类号： G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/50016

摘要： The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.

摘要翻译： 本发明能够筛选所谓的可变保留时间（VRT）故障，即由于诸如随机电报噪声的数据保留时间的波动而在DRAM中发生的保留故障。 在芯片的所有存储单元上重复用于检查数据保留功能的暂停/刷新测试，使得可能发生由于数据保留能力的随机波动而发生的保留故障的存储单元被进行筛选。

公开(公告)号：US20050098813A1

公开(公告)日：2005-05-12

申请号：US10931119

申请日：2004-09-01

申请人： Tomoko Sekiguchi ,  Shinichiro Kimura ,  Renichi Yamada ,  Kikuo Watanabe ,  Hiroshi Miki ,  Kenichi Takeda

发明人： Tomoko Sekiguchi ,  Shinichiro Kimura ,  Renichi Yamada ,  Kikuo Watanabe ,  Hiroshi Miki ,  Kenichi Takeda

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/1079 ,  H01L29/6656 ,  H01L29/7835

摘要： Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.

摘要翻译： 这里公开了具有在存储单元中具有MISFET阈值电压的较小散射并具有良好的电容保持性的DRAM的半导体器件，以及半导体器件的制造方法。 在光氧化之前，在栅电极的侧壁上形成抗氧化膜，从而抑制栅电极的侧壁的氧化，并且在不对称扩散区域结构中减少形成在侧壁上的膜的厚度的散射 使数据线一侧的n型半导体区域和p型半导体区域的杂质浓度比n型半导体区域和p型半导体区域的杂质浓度相对高于 电容器。