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    Process cell for an N-dimensional processor array having a single input element with 2N data inputs, memory, and full function arithmetic logic unit
    1.
    发明授权
    Process cell for an N-dimensional processor array having a single input element with 2N data inputs, memory, and full function arithmetic logic unit 失效
    具有2N数据输入，存储器和全功能算术逻辑单元的单个输入单元的N维处理器阵列的处理单元

    公开(公告)号：US5157785A

    公开(公告)日：1992-10-20

    申请号：US530027

    申请日：1990-05-29

    申请人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

    发明人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

    IPC分类号： G06F15/16 ,  G06F15/80

    CPC分类号： G06F15/8015 ,  G06F15/803

    摘要： A multi-dimensional processor cell and processor array with massively parallel input/output includes a processor array having a plurality of processor cells interconnected to form an N-dimensional array. The system includes a first group of processor cells having 2N dimensionally adjacent processor cells. At least one input/output device is connected to a surplus data signal port of a second group of processor cells each having fewer than 2N dimensionally adjacent processor cells, for providing massively parallel input/output between the multi-dimensional processor array and the input/output device. The processor system also includes a front end processor for providing processor array instructions in response to application programs running on the front end processor. A processor cell controller, responsive to the processor array commands, broadcasts a sequence of processor cell instructions to all of the processor cells of the multi-dimensional processor array.

    摘要翻译： 具有大规模并行输入/输出的多维处理器单元和处理器阵列包括具有互连以形成N维阵列的多个处理器单元的处理器阵列。 该系统包括具有2N维度相邻的处理器单元的第一组处理器单元。 至少一个输入/输出设备连接到每个具有少于2N个尺寸相邻的处理器单元的第二组处理器单元的剩余数据信号端口，用于在多维处理器阵列和输入/输出设备之间提供大规模并行输入/输出， 输出设备。 处理器系统还包括前端处理器，用于响应于在前端处理器上运行的应用程序提供处理器阵列指令。 响应于处理器阵列命令的处理器单元控制器向多维处理器阵列的所有处理器单元广播一系列处理器单元指令。

    Fault resilient/fault tolerant computing
    2.
    发明授权
    Fault resilient/fault tolerant computing 失效
    故障恢复/容错计算

    公开(公告)号：US5600784A

    公开(公告)日：1997-02-04

    申请号：US405193

    申请日：1995-03-16

    申请人： Thomas D. Bissett ,  Richard D. Fiorentino ,  Robert M. Glorioso ,  Diane T. McCauley ,  James D. McCollum ,  Glenn A. Tremblay

    发明人： Thomas D. Bissett ,  Richard D. Fiorentino ,  Robert M. Glorioso ,  Diane T. McCauley ,  James D. McCollum ,  Glenn A. Tremblay

    IPC分类号： G06F11/18 ,  G06F1/04 ,  G06F1/14 ,  G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/10 ,  G06F13/14 ,  G06F15/16 ,  G06F15/76 ,  G01R31/28

    CPC分类号： G06F11/1658 ,  G06F1/14 ,  G06F11/1645 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/2005 ,  G06F11/2017 ,  G06F11/1641 ,  G06F11/185

    摘要： In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing elements.Computer systems include one or more controllers and at least two computing elements. System is provided for intercepting I/O operations by the computing elements and transmitting them to the one or more controllers.

    摘要翻译： 在第一方面中，一种同步至少两个计算元件的方法，每个计算元件具有与其它计算元件的时钟异步工作的时钟，包括从由所述另一个计算元件产生的一组信号中选择一个或多个指定为元时间信号的信号 计算元件，监视所述计算元件以通过所述计算元件之一检测所选择的信号的产生，等待所述其他计算元件产生所选择的信号，向所述计算元件中的每一个发送等价的时间更新，以及更新所述时钟 的计算元素基于时间更新。 在第二方面，通过将第一处理器指定为计算元件，指定作为控制器的第二处理器，连接计算元件和控制器以产生模块对，并连接至少两个模块化 成对产生故障恢复或容错计算机。 计算机的每个计算元件执行与其它计算元件相同数量的循环的所有指令。 计算机系统包括一个或多个控制器和至少两个计算元件。 提供系统用于通过计算元件截取I / O操作并将其发送到一个或多个控制器。

    Processor array of N-dimensions which is physically reconfigurable into N-1
    5.
    发明授权
    Processor array of N-dimensions which is physically reconfigurable into N-1 失效
    具有N-1或更少尺寸的N维的N维处理器阵列

    公开(公告)号：US5133073A

    公开(公告)日：1992-07-21

    申请号：US529962

    申请日：1990-05-29

    申请人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

    发明人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

    IPC分类号： G06F15/16 ,  G06F15/173 ,  G06F15/80

    CPC分类号： G06F15/17343 ,  G06F15/803

    摘要： A reconfigurable multi-dimensional processor array for processing multi-dimensionally structured data includes a plurality of processor cells arranged in N dimensions and having a plurality of N-1 dimensional processor subarrays. Each of the processor cells has 2N data signal ports operative for forming data signal paths for transmitting and receiving data to and from 2N adjacent processor cells or data communication devices. Each of the N-1 dimensional processor subarrays includes a selected group of processor cells coupled to fewer than 2N other processor cells or data communications devices. Each of the selected group of processor cells includes at least one uncoupled data signal port. An intermediary connection couples selected uncoupled data signal ports from at least a first N-1 dimensional processor subarray to selected uncoupled data signal ports from at least a second N-1 dimensional processor subarray, to form selected data signal paths between selected processor cells within the at least first and second N-1 dimensional processor subarrays.

    摘要翻译： 用于处理多维结构化数据的可重构多维处理器阵列包括以N维排列并具有多个N-1维处理器子阵列的多个处理器单元。 每个处理器单元具有2N个数据信号端口，用于形成用于向2N个相邻的处理器单元或数据通信设备发送和接收数据的数据信号路径。 N-1维处理器子阵列中的每一个包括耦合到少于2N个其他处理器单元或数据通信设备的选定组的处理器单元。 所选择的一组处理器单元中的每一个包括至少一个非耦合数据信号端口。 中间连接将所选择的非耦合数据信号端口从至少第一N-1维处理器子阵列耦合到来自至少第二N-1维处理器子阵列的选择的未耦合数据信号端口，以在所述第一N-1维处理器子阵列内的选定处理器单元之间形成所选择的数据信号路径 至少第一和第二N-1维处理器子阵列。

    Fault resilient/fault tolerant computing
    6.
    发明授权
    Fault resilient/fault tolerant computing 失效
    故障恢复/容错计算

    公开(公告)号：US6038685A

    公开(公告)日：2000-03-14

    申请号：US934747

    申请日：1997-09-22

    申请人： Thomas Dale Bissett ,  Richard D. Fiorentino ,  Robert M. Glorioso ,  Diane T. McCauley ,  James D. McCollum ,  Glenn A. Tremblay ,  Mario Troiani

    发明人： Thomas Dale Bissett ,  Richard D. Fiorentino ,  Robert M. Glorioso ,  Diane T. McCauley ,  James D. McCollum ,  Glenn A. Tremblay ,  Mario Troiani

    IPC分类号： G06F11/18 ,  G06F1/04 ,  G06F1/14 ,  G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/10 ,  G06F13/14 ,  G06F15/16 ,  G06F15/76

    CPC分类号： G06F11/1658 ,  G06F1/14 ,  G06F11/1645 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/181 ,  G06F11/2005 ,  G06F11/2017 ,  G06F11/1641 ,  G06F11/185

    摘要： In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing elements.Computer systems include one or more controllers and at least two computing elements. Means are provided for intercepting I/O operations by the computing elements and transmitting them to the one or more controllers.

    摘要翻译： 在第一方面中，一种同步至少两个计算元件的方法，每个计算元件具有与其它计算元件的时钟异步工作的时钟，包括从由所述另一个计算元件产生的一组信号中选择一个或多个指定为元时间信号的信号 计算元件，监视所述计算元件以通过所述计算元件之一检测所选择的信号的产生，等待所述其他计算元件产生所选择的信号，向所述计算元件中的每一个发送等价的时间更新，以及更新所述时钟 的计算元素基于时间更新。 在第二方面，通过将第一处理器指定为计算元件，指定作为控制器的第二处理器，连接计算元件和控制器以产生模块对，并连接至少两个模块化 成对产生故障恢复或容错计算机。 计算机的每个计算元件执行与其它计算元件相同数量的循环的所有指令。 计算机系统包括一个或多个控制器和至少两个计算元件。 提供了用于通过计算元件截取I / O操作并将其发送到一个或多个控制器的手段。