公开(公告)号：US20060029792A1

公开(公告)日：2006-02-09

申请号：US11005547

申请日：2004-12-06

申请人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

发明人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

IPC分类号： B05D7/00 ,  C23C16/00 ,  B32B5/16

CPC分类号： C30B29/406 ,  B82Y10/00 ,  B82Y30/00 ,  C30B25/00 ,  C30B25/14 ,  C30B29/40 ,  C30B29/48 ,  C30B29/52 ,  C30B29/605 ,  Y10T428/25

摘要： Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

摘要翻译： 在没有掩模制造并允许任何程度的晶格失配的情况下在缓冲层上制造自组装纳米颗粒的方法; 即包含III-V族，II-VI族或IV-VI族的二元，三元或四元纳米颗粒。 该方法包括施加缓冲层的第一步骤，打开吹扫气体以将第一反应物调节到较低的第一流速的第二步骤，然后将第二反应物供应到缓冲层以形成富金属的岛 以及再次打开吹扫气体以将第一反应物调节到较高的第二流量的缓冲层上的第三步骤。 在富金属的岛上形成二元，三元或四元III-V，II-VI和IV-IV半导体材料的纳米颗粒。 然后在高温下在第一反应物流下重结晶形成高质量的纳米颗粒。

公开(公告)号：US06503578B1

公开(公告)日：2003-01-07

申请号：US09565473

申请日：2000-05-05

申请人： Pey-Shiun Yeh ,  Jyh-Shin Chen ,  Cheng-Chung Jaing ,  Hsiang-Ming Tseng ,  Long-Sheng Liao ,  Ming-Chih Lee

发明人： Pey-Shiun Yeh ,  Jyh-Shin Chen ,  Cheng-Chung Jaing ,  Hsiang-Ming Tseng ,  Long-Sheng Liao ,  Ming-Chih Lee

IPC分类号： C23C1428

CPC分类号： C23C14/3435 ,  C23C14/0629 ,  C23C14/28

摘要： Zincselenide (ZnSe) thin films were grown on quartz glass and GaAs(100) substrates by continuous wave (CW) CO2 laser with ion beam assisted deposition. The ZnSe thin films are applied for multilayer anti-reflection coatings and blue light emitting devices. There are advantages to this technique over the Ion-Beam coating, MBE, MOCVD and PLD methods for fabricating layered semiconductors. It is cheaper and safer than Ion-Beam coating, MBE, MOCVD and others. It is cheaper and safer to heat the target locally by using a continuous wave laser so that contaminations and heat radiation are reduced. It is also cheaper and safer to avoid the splash of PLD.

摘要翻译： 使用离子束辅助沉积的连续波（CW）CO2激光将石英玻璃和GaAs（100）衬底上的硒化锌（ZnSe）薄膜生长。 ZnSe薄膜被应用于多层抗反射涂层和蓝色发光器件。 对于用于制造层状半导体的离子束涂层，MBE，MOCVD和PLD方法，这种技术有优势。 它比Ion-Beam涂层，MBE，MOCVD等更便宜和更安全。 通过使用连续波激光器来局部加热靶，从而降低污染物和热辐射是更便宜和更安全的。 避免PLD飞溅也更便宜，更安全。

公开(公告)号：US07294202B2

公开(公告)日：2007-11-13

申请号：US11005547

申请日：2004-12-06

申请人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

发明人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

IPC分类号： C30B29/60

CPC分类号： C30B29/406 ,  B82Y10/00 ,  B82Y30/00 ,  C30B25/00 ,  C30B25/14 ,  C30B29/40 ,  C30B29/48 ,  C30B29/52 ,  C30B29/605 ,  Y10T428/25

摘要： Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

摘要翻译： 在没有掩模制造并允许任何程度的晶格失配的情况下在缓冲层上制造自组装纳米颗粒的方法; 即包含III-V族，II-VI族或IV-VI族的二元，三元或四元纳米颗粒。 该方法包括施加缓冲层的第一步骤，打开吹扫气体以将第一反应物调节到较低的第一流速的第二步骤，然后将第二反应物供应到缓冲层以形成富金属的岛 以及再次打开吹扫气体以将第一反应物调节到较高的第二流量的缓冲层上的第三步骤。 在富金属的岛上形成二元，三元或四元III-V，II-VI和IV-IV半导体材料的纳米颗粒。 然后在高温下在第一反应物流下重结晶形成高质量的纳米颗粒。

公开(公告)号：US5193202A

公开(公告)日：1993-03-09

申请号：US529947

申请日：1990-05-29

申请人： James H. Jackson ,  Ming-Chih Lee

发明人： James H. Jackson ,  Ming-Chih Lee

IPC分类号： G06F12/08 ,  G06F15/16 ,  G06F15/80

CPC分类号： G06F15/8007

摘要： A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than the number of nodes in the problem space. The system partitions the memory of each physical processor cell into several equal sections, each section being associated with one node of the problem space. The instruction generator then produces a sequence of processor cell instructions for each node of the given problem space, with appropriate address modifications for each sequence of instructions provided by an address relocation circuit.

摘要翻译： 一种并行处理系统，包括虚拟处理指令和地址生成器，用于将处理器单元指令生成到并行处理阵列，例如多维处理器阵列，其可以具有比问题空间中的节点数更少的处理器单元。 系统将每个物理处理器单元的存储器分成几个相等的部分，每个部分与问题空间的一个节点相关联。 然后，指令产生器针对给定问题空间的每个节点产生一系列处理器单元指令，对由地址重定位电路提供的每个指令序列进行适当的地址修改。

公开(公告)号：US5133073A

公开(公告)日：1992-07-21

申请号：US529962

申请日：1990-05-29

申请人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

发明人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

IPC分类号： G06F15/16 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F15/17343 ,  G06F15/803

摘要： A reconfigurable multi-dimensional processor array for processing multi-dimensionally structured data includes a plurality of processor cells arranged in N dimensions and having a plurality of N-1 dimensional processor subarrays. Each of the processor cells has 2N data signal ports operative for forming data signal paths for transmitting and receiving data to and from 2N adjacent processor cells or data communication devices. Each of the N-1 dimensional processor subarrays includes a selected group of processor cells coupled to fewer than 2N other processor cells or data communications devices. Each of the selected group of processor cells includes at least one uncoupled data signal port. An intermediary connection couples selected uncoupled data signal ports from at least a first N-1 dimensional processor subarray to selected uncoupled data signal ports from at least a second N-1 dimensional processor subarray, to form selected data signal paths between selected processor cells within the at least first and second N-1 dimensional processor subarrays.

摘要翻译： 用于处理多维结构化数据的可重构多维处理器阵列包括以N维排列并具有多个N-1维处理器子阵列的多个处理器单元。 每个处理器单元具有2N个数据信号端口，用于形成用于向2N个相邻的处理器单元或数据通信设备发送和接收数据的数据信号路径。 N-1维处理器子阵列中的每一个包括耦合到少于2N个其他处理器单元或数据通信设备的选定组的处理器单元。 所选择的一组处理器单元中的每一个包括至少一个非耦合数据信号端口。 中间连接将所选择的非耦合数据信号端口从至少第一N-1维处理器子阵列耦合到来自至少第二N-1维处理器子阵列的选择的未耦合数据信号端口，以在所述第一N-1维处理器子阵列内的选定处理器单元之间形成所选择的数据信号路径 至少第一和第二N-1维处理器子阵列。

公开(公告)号：US5157785A

公开(公告)日：1992-10-20

申请号：US530027

申请日：1990-05-29

申请人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

发明人： James H. Jackson ,  Ming-Chih Lee ,  Mark R. LaForest ,  Richard D. Fiorentino

IPC分类号： G06F15/16 ,  G06F15/80

CPC分类号： G06F15/8015 ,  G06F15/803

摘要： A multi-dimensional processor cell and processor array with massively parallel input/output includes a processor array having a plurality of processor cells interconnected to form an N-dimensional array. The system includes a first group of processor cells having 2N dimensionally adjacent processor cells. At least one input/output device is connected to a surplus data signal port of a second group of processor cells each having fewer than 2N dimensionally adjacent processor cells, for providing massively parallel input/output between the multi-dimensional processor array and the input/output device. The processor system also includes a front end processor for providing processor array instructions in response to application programs running on the front end processor. A processor cell controller, responsive to the processor array commands, broadcasts a sequence of processor cell instructions to all of the processor cells of the multi-dimensional processor array.

摘要翻译： 具有大规模并行输入/输出的多维处理器单元和处理器阵列包括具有互连以形成N维阵列的多个处理器单元的处理器阵列。 该系统包括具有2N维度相邻的处理器单元的第一组处理器单元。 至少一个输入/输出设备连接到每个具有少于2N个尺寸相邻的处理器单元的第二组处理器单元的剩余数据信号端口，用于在多维处理器阵列和输入/输出设备之间提供大规模并行输入/输出， 输出设备。 处理器系统还包括前端处理器，用于响应于在前端处理器上运行的应用程序提供处理器阵列指令。 响应于处理器阵列命令的处理器单元控制器向多维处理器阵列的所有处理器单元广播一系列处理器单元指令。

公开(公告)号：US20130218473A1

公开(公告)日：2013-08-22

申请号：US13592010

申请日：2012-08-22

申请人： Chua-Chin Wang ,  Chia-Hao Hsu ,  I-Yu Huang ,  Yun-Chi Chen ,  Yue-Da Tsai ,  Ming-Chih Lee

发明人： Chua-Chin Wang ,  Chia-Hao Hsu ,  I-Yu Huang ,  Yun-Chi Chen ,  Yue-Da Tsai ,  Ming-Chih Lee

IPC分类号： G06F19/00

CPC分类号： G01N33/6848

摘要： A frequency shift detector includes a digital control unit, a digital/analog converter, a reagent concentration detecting circuit and a frequency difference generator, wherein the digital control unit includes a control circuit and a direct digital frequency synthesizer electrically connected with the control circuit, and the control circuit comprises a reset terminal and a pulse input terminal. The digital control unit proceeds with accurate concentration detection for various samples borne on the reagent concentration detecting circuit.

摘要翻译： 一种频移检测器，包括数字控制单元，数字/模拟转换器，试剂浓度检测电路和频差发生器，其中数字控制单元包括与控制电路电连接的控制电路和直接数字频率合成器，以及 控制电路包括复位端和脉冲输入端。 数字控制单元对于试剂浓度检测电路上承载的各种样品进行准确的浓度检测。

公开(公告)号：US07884687B2

公开(公告)日：2011-02-08

申请号：US11807517

申请日：2007-05-29

申请人： Ming-Chih Lee

发明人： Ming-Chih Lee

IPC分类号： H03H7/18 ,  H03H7/21

CPC分类号： H04L25/0266 ,  H01F2017/0093 ,  H01F2019/085

摘要： A magnetic interface circuit (100) includes a pair of channels (101, 102) and an absorb network (3). Each channel includes a 3-wire common mode choke (2) having a middle tap (21), and an isolation transformer (1) connected with the 3-wire common mode choke. The isolation transformer has a primary winding (11) and a secondary winding (12) each having a pair of first output taps (111, 121) and a first center tap (13, 14). The absorb network includes a bridge rectifying circuit (4) adapted for converting an electrical current. Each bridge rectifying circuit has a pair of input taps (45, 46) each connected with corresponding center taps of the isolation transformers, and a pair of output taps (47, 48).

摘要翻译： 磁接口电路（100）包括一对通道（101,102）和吸收网络（3）。 每个通道包括具有中间抽头（21）的3线共模扼流圈（2）和与3线共模扼流圈连接的隔离变压器（1）。 隔离变压器具有初级绕组（11）和次级绕组（12），每个绕组具有一对第一输出抽头（111,121）和第一中心抽头（13,14）。 吸收网络包括适于转换电流的桥式整流电路（4）。 每个桥式整流电路具有一对与隔离变压器的相应中心抽头相连的输入抽头（45,46）和一对输出抽头（47,48）。

公开(公告)号：US20070297201A1

公开(公告)日：2007-12-27

申请号：US11807517

申请日：2007-05-29

申请人： Ming-Chih Lee

发明人： Ming-Chih Lee

IPC分类号： H02M3/335

CPC分类号： H04L25/0266 ,  H01F2017/0093 ,  H01F2019/085

摘要： A magnetic interface circuit (100) includes a pair of channels (101, 102) and an absorb network (3). Each channel includes a 3-wire common mode choke (2) having a middle tap (21), and an isolation transformer (1) connected with the 3-wire common mode choke. The isolation transformer has a primary winding (11) and a secondary winding (12) each having a pair of first output taps (111, 121) and a first center tap (13, 14). The absorb network includes a bridge rectifying circuit (4) adapted for converting an electrical current. Each bridge rectifying circuit has a pair of input taps (45, 46) each connected with corresponding center taps of the isolation transformers, and a pair of output taps (47, 48).

摘要翻译： 磁接口电路（100）包括一对通道（101,102）和吸收网络（3）。 每个通道包括具有中间抽头（21）的3线共模扼流圈（2）和与3线共模扼流圈连接的隔离变压器（1）。 隔离变压器具有初级绕组（11）和次级绕组（12），每个绕组具有一对第一输出抽头（111,121）和第一中心抽头（13,14）。 吸收网络包括适于转换电流的桥式整流电路（4）。 每个桥式整流电路具有一对与隔离变压器的相应中心抽头相连的输入抽头（45,46）和一对输出抽头（47,48）。

公开(公告)号：US20070015402A1

公开(公告)日：2007-01-18

申请号：US11485881

申请日：2006-07-13

申请人： Ming-Chih Lee

发明人： Ming-Chih Lee

IPC分类号： H01R13/66

CPC分类号： H01R13/6658 ,  H01R13/6625 ,  H01R13/6633 ,  H01R13/6691 ,  H01R13/719 ,  H01R24/64 ,  H01R2201/04

摘要： A modular connector for electrically connecting a modular plug to a mother board includes an insulative housing having a vertical front mating face and an electrical module mounted in the housing. The electrical module includes a front PCB parallel the mating face, two mutual parallel second electric circuit boards perpendicularly connecting to the front PCB, and a number of magnetic coils directly mounted on the rear PCBs.

摘要翻译： 用于将模块化插头电连接到母板的模块化连接器包括具有垂直前配合面和安装在壳体中的电气模块的绝缘壳体。 电气模块包括平行配合面的前PCB，垂直连接到前PCB的两个相互平行的第二电路板和直接安装在后PCB上的多个磁线圈。