公开(公告)号：US20140007029A1

公开(公告)日：2014-01-02

申请号：US13536694

申请日：2012-06-28

申请人： Robert E. Boone ,  Puneet Sharma ,  Matthew A. Thompson

发明人： Robert E. Boone ,  Puneet Sharma ,  Matthew A. Thompson

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.

摘要翻译： 用于评估集成电路设计中的放置上下文敏感度的公开的方法包括访问包括标准单元的数据库的标准单元库，并且为每个标准单元确定生成边界数据。 标准单元的边界数据表示位于标准单元的边界区域内的特征的布局。 该方法包括如果边界数据相同以合并或合并任何两个标准单元的边界数据，以确定边界区域的典型或最小集合。 所公开的方法还包括枚举和评估规范边界区域对的所有组合，并且响应于识别基于接近度的灵敏度或异常，修改，表示或以其他方式修复与边界对应的适用的一个或多个标准单元 引起异常的区域组合。

公开(公告)号：US06593226B2

公开(公告)日：2003-07-15

申请号：US09906874

申请日：2001-07-17

申请人： Edward O. Travis ,  Aykut Dengi ,  Sejal Chheda ,  Tat-Kwan Yu ,  Mark S. Roberton ,  Ruiqi Tian ,  Robert E. Boone ,  Alfred J. Reich

发明人： Edward O. Travis ,  Aykut Dengi ,  Sejal Chheda ,  Tat-Kwan Yu ,  Mark S. Roberton ,  Ruiqi Tian ,  Robert E. Boone ,  Alfred J. Reich

IPC分类号： H01L214763

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  Y10S438/926

摘要： Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

公开(公告)号：US08661393B2

公开(公告)日：2014-02-25

申请号：US13536694

申请日：2012-06-28

申请人： Robert E. Boone ,  Puneet Sharma ,  Matthew A. Thompson

发明人： Robert E. Boone ,  Puneet Sharma ,  Matthew A. Thompson

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.

摘要翻译： 用于评估集成电路设计中的放置上下文敏感度的公开的方法包括访问包括标准单元的数据库的标准单元库，并且为每个标准单元确定生成边界数据。 标准单元的边界数据表示位于标准单元的边界区域内的特征的布局。 该方法包括如果边界数据相同以合并或合并任何两个标准单元的边界数据，以确定边界区域的典型或最小集合。 所公开的方法还包括列举和评估规范边界区域对的所有组合，并且响应于识别基于接近度的灵敏度或异常，修改，表示或以其他方式补救对应于边界的可应用的一个或多个标准单元 引起异常的区域组合。

公开(公告)号：US06818362B1

公开(公告)日：2004-11-16

申请号：US10782566

申请日：2004-02-19

申请人： Kevin D. Lucas ,  Robert E. Boone ,  Lloyd C. Litt ,  Wei E. Wu

发明人： Kevin D. Lucas ,  Robert E. Boone ,  Lloyd C. Litt ,  Wei E. Wu

IPC分类号： G03F900

CPC分类号： G03F1/26 ,  G03F1/30 ,  G03F1/68

摘要： A method of generating a design of a reticle for a photolithography process. The reticle may include phase shift features, binary features, and mixed features. The method includes generating a reticle design from a pattern layout and then optimizing the reticle design. In some examples, generating the reticle design includes binning the features of the layout based on feature width. Examples of optimization operations include an over/under operation, an under/over operation, a feature segment expansion operation, a feature edge portion conversation from a binary portion to a phase shift portion, a corner binary segment expansion, a discontinuity removal operation, and a feature dimension change operation that includes a determination of a Mask Error Factor (MEF).

摘要翻译： 一种产生光刻工艺的掩模版设计的方法。 标线片可以包括相移特征，二进制特征和混合特征。 该方法包括从图案布局生成掩模版设计，然后优化掩模版设计。 在一些示例中，生成掩模版设计包括基于特征宽度来组合布局的特征。 优化操作的示例包括过/下操作，下/过操作，特征段扩展操作，从二进制部分到相移部分的特征边缘部分对话，角二进制段扩展，不连续删除操作和 特征尺寸变化操作，其包括掩模误差因子（MEF）的确定。

公开(公告)号：US20080250374A1

公开(公告)日：2008-10-09

申请号：US12067583

申请日：2005-09-20

申请人： Kevin D. Lucas ,  Robert E. Boone ,  Karl Wimmer ,  Kyle Patterson

发明人： Kevin D. Lucas ,  Robert E. Boone ,  Karl Wimmer ,  Kyle Patterson

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method is provided for making an integrated circuit. Cell representing a layout of a set of features, is divided into at least a first region and a second region. Optical Proximity Correction is carried out on at least the first region of cell. One or more instances of cell are located to define IC prior to carrying out final OPC optimisation on the second regions of each cell in the defined IC.

摘要翻译： 提供了一种制造集成电路的方法。 表示一组特征的布局的单元被划分为至少第一区域和第二区域。 至少在细胞的第一区域进行光学邻近校正。 定位单元的一个或多个实例以在对所定义的IC中的每个单元的第二区域进行最终OPC优化之前定义IC。

公开(公告)号：US07284231B2

公开(公告)日：2007-10-16

申请号：US11018637

申请日：2004-12-21

申请人： Kevin D. Lucas ,  Robert E. Boone ,  Mehul D. Shroff ,  Kirk J. Strozewski ,  Chi-Min Yuan ,  Jason T. Porter

发明人： Kevin D. Lucas ,  Robert E. Boone ,  Mehul D. Shroff ,  Kirk J. Strozewski ,  Chi-Min Yuan ,  Jason T. Porter

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

摘要翻译： 一种用于改进设计的可制造性的方法包括在布局设计的多个交互层上执行空间或外壳检查，然后使用所得到的空间或外壳数据来移动改变的设计数据库中的预定特征边缘以降低特征宽度，特征 图案的空间或特征外壳图案比设计的小。 在一些实施例中，晶片电路图案中的大尺寸特征比在设计的数据库中绘制的特征更大。 在一些实施例中，用于提高设计的可制造性的方法被存储在计算机可读存储介质上。