-
公开(公告)号：US09658861B2
公开(公告)日：2017-05-23
申请号：US13993310
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F9/44 , G06F15/177
CPC分类号： G06F9/4405 , G06F15/177
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.
-
2.发明授权Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit 有权用于多核处理单元的高级可编程中断控制器标识符（APIC ID）分配公开(公告)号：US09372816B2
公开(公告)日：2016-06-21
申请号：US13994104
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
CPC分类号： G06F13/24
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.
摘要翻译： 在重新启动或重启包含多核处理器的系统之后，多核处理器可以为每个活动和合格的核心分配唯一的高级可编程中断控制器（APIC）标识符（ID）。 初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。 初始化逻辑可以检测多个处理核心中的每个处理核心的属性符合分配APIC ID的资格，或者不符合APIC ID分配的资格。
-
公开(公告)号：US06385735B1
公开(公告)日：2002-05-07
申请号：US08990526
申请日：1997-12-15
IPC分类号： G06F104
CPC分类号： G06F1/08
摘要： A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.
摘要翻译： 用于限制处理器时钟频率的方法和装置包括超频防止电路。 超频防止电路包括具有可编程可熔元件的频率限制电路。 频率限制电路基于每个可熔元件的状态输出识别最大处理器时钟频率的信号。 比较器电路将所选择的处理器时钟频率与最大处理器时钟频率进行比较，以确定所选择的处理器时钟频率是否被允许。 如果所选择的处理器时钟频率不被允许，则处理器不允许以选定的时钟频率工作。
-
公开(公告)号：US20140006767A1
公开(公告)日：2014-01-02
申请号：US13993310
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F9/44
CPC分类号： G06F9/4405 , G06F15/177
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.
摘要翻译： 在重新启动或重新启动包括多核处理器的系统之后，多核处理器可以将一个核心分配为引导带处理器（BSP）。 初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。 初始化逻辑可以检测多个处理核心中的每一个的属性被认定为被分配为BSP，或者不符合被分配为BSP的资格。 初始化逻辑可以至少部分地基于状态来检测作为活动处理核心的互连中的多个处理核心的最后处理核心，并且至少部分地基于该属性将其分配为BSP。 在各种实施例中，初始化信息可以将最后的处理核分配为BSP。
-
公开(公告)号：US07395449B2
公开(公告)日：2008-07-01
申请号：US11593889
申请日：2006-11-06
IPC分类号： G06F1/04
CPC分类号： G06F1/08
摘要： A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.
摘要翻译： 用于限制处理器时钟频率的方法和装置包括超频防止电路。 超频防止电路包括具有可编程可熔元件的频率限制电路。 频率限制电路基于每个可熔元件的状态输出识别最大处理器时钟频率的信号。 比较器电路将所选择的处理器时钟频率与最大处理器时钟频率进行比较，以确定所选择的处理器时钟频率是否被允许。 如果所选择的处理器时钟频率不被允许，则处理器不允许以选定的时钟频率工作。
-
公开(公告)号：US07134037B2
公开(公告)日：2006-11-07
申请号：US10640752
申请日：2003-08-13
IPC分类号： G06F1/04
CPC分类号： G06F1/08
摘要： A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.
-
7.发明申请ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT 有权高级可编程中断控制器标识符（APIC ID）多核处理单元的分配公开(公告)号：US20140156896A1
公开(公告)日：2014-06-05
申请号：US13994104
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.
摘要翻译： 在重新启动或重启包含多核处理器的系统之后，多核处理器可以为每个活动和合格的核心分配唯一的高级可编程中断控制器（APIC）标识符（ID）。 初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。 初始化逻辑可以检测多个处理核心中的每个处理核心的属性符合分配APIC ID的资格，或者不符合APIC ID分配的资格。
-
公开(公告)号：US06633993B2
公开(公告)日：2003-10-14
申请号：US10051051
申请日：2002-01-22
IPC分类号： G06F104
CPC分类号： G06F1/08
摘要： A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.
摘要翻译： 用于限制处理器时钟频率的方法和装置包括超频防止电路。 超频防止电路包括具有可编程可熔元件的频率限制电路。 频率限制电路基于每个可熔元件的状态输出识别最大处理器时钟频率的信号。 比较器电路将所选择的处理器时钟频率与最大处理器时钟频率进行比较，以确定所选择的处理器时钟频率是否被允许。 如果所选择的处理器时钟频率不被允许，则处理器不允许以选定的时钟频率工作。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.013 秒)
